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Commit 17a13590 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v4.4' of git://git.linaro.org/people/ulf.hansson/mmc 

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Add new API to set VCCQ voltage - mmc_regulator_set_vqmmc()
   - Add new ioctl to allow userspace to send multi commands
   - Wait for card busy signalling before starting SDIO requests
   - Remove MMC_CLKGATE
   - Enable tuning for DDR50 mode
   - Some code clean-up/improvements to mmc pwrseq
   - Use highest priority for eMMC restart handler
   - Add DT bindings for eMMC hardware reset support
   - Extend the mmc_send_tuning() API
   - Improve ios show for debugfs
   - A couple of code optimizations

  MMC host:
   - Some generic OF improvements
   - Various code clean-ups
   - sirf: Add support for DDR50
   - sunxi: Add support for card busy detection
   - mediatek: Use MMC_CAP_RUNTIME_RESUME
   - mediatek: Add support for eMMC HW-reset
   - mediatek: Add support for HS400
   - dw_mmc: Convert to use the new mmc_regulator_set_vqmmc() API
   - dw_mmc: Add external DMA interface support
   - dw_mmc: Some various improvements
   - dw_mmc-rockchip: MMC tuning with the clock phase framework
   - sdhci: Properly clear IRQs during resume
   - sdhci: Enable tuning for DDR50 mode
   - sdhci-of-esdhc: Use IRQ mode for card detection
   - sdhci-of-esdhc: Support both BE and LE host controller
   - sdhci-pci: Build o2micro support in the same module
   - sdhci-pci: Support for new Intel host controllers
   - sdhci-acpi: Support for new Intel host controllers"

* tag 'mmc-v4.4' of git://git.linaro.org/people/ulf.hansson/mmc: (73 commits)
  mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode
  mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register
  mmc: dw_mmc: NULL dereference in error message
  mmc: pwrseq: Use highest priority for eMMC restart handler
  mmc: mediatek: add HS400 support
  mmc: mmc: extend the mmc_send_tuning()
  mmc: mediatek: add implement of ops->hw_reset()
  mmc: mediatek: fix got GPD checksum error interrupt when data transfer
  mmc: mediatek: change the argument "ddr" to "timing"
  mmc: mediatek: make cmd_ints_mask to const
  mmc: dt-bindings: update Mediatek MMC bindings
  mmc: core: Add DT bindings for eMMC hardware reset support
  mmc: omap_hsmmc: Enable omap_hsmmc for Keystone 2
  mmc: sdhci-acpi: Add more ACPI HIDs for Intel controllers
  mmc: sdhci-pci: Add more PCI IDs for Intel controllers
  arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
  arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
  arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
  mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
  ...
parents 66b01996 7cc8d580

Documentation/devicetree/bindings/mmc/fsl-esdhc.txt

+2 −0
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ Optional properties: 
  - voltage-ranges : two cells are required, first cell specifies minimum

    slot voltage (mV), second cell specifies maximum slot voltage (mV).

    Several ranges could be specified.

  - little-endian : If the host controller is little-endian mode, specify

    this property. The default endian mode is big-endian.



Example:

Documentation/devicetree/bindings/mmc/mmc.txt

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ Optional properties: 
- sd-uhs-sdr104: SD UHS SDR104 speed is supported

- sd-uhs-ddr50: SD UHS DDR50 speed is supported

- cap-power-off-card: powering off the card is safe

- cap-mmc-hw-reset: eMMC hardware reset is supported

- cap-sdio-irq: enable SDIO IRQ signalling on this interface

- full-pwr-cycle: full power cycle of the card is supported

- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported

Documentation/devicetree/bindings/mmc/mtk-sd.txt

+10 −1
Original line number Diff line number Diff line
@@ -17,6 +17,11 @@ Required properties: 
- vmmc-supply: power to the Core

- vqmmc-supply: power to the IO



Optional properties:

- assigned-clocks: PLL of the source clock

- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock

- hs400-ds-delay: HS400 DS delay setting



Examples:

mmc0: mmc@11230000 {

	compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
@@ -24,9 +29,13 @@ mmc0: mmc@11230000 { 
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;

	vmmc-supply = <&mt6397_vemc_3v3_reg>;

	vqmmc-supply = <&mt6397_vio18_reg>;

	clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>;

	clocks = <&pericfg CLK_PERI_MSDC30_0>,

	         <&topckgen CLK_TOP_MSDC50_0_H_SEL>;

	clock-names = "source", "hclk";

	pinctrl-names = "default", "state_uhs";

	pinctrl-0 = <&mmc0_pins_default>;

	pinctrl-1 = <&mmc0_pins_uhs>;

	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;

	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;

	hs400-ds-delay = <0x14015>;

};

Documentation/devicetree/bindings/mmc/renesas,mmcif.txt

+3 −2
Original line number Diff line number Diff line
@@ -6,11 +6,12 @@ and the properties used by the MMCIF device. 


Required properties:



- compatible: must contain one of the following

- compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a

  fallback. Examples with <soctype> are:

	- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs

	- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs

	- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs

	- "renesas,sh-mmcif" for the generic MMCIF

	- "renesas,mmcif-r8a7794" for the MMCIF found in r8a7794 SoCs



- clocks: reference to the functional clock

Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt

+13 −0
Original line number Diff line number Diff line
@@ -14,6 +14,19 @@ Required Properties: 
							before RK3288

	- "rockchip,rk3288-dw-mshc": for Rockchip RK3288



Optional Properties:

* clocks: from common clock binding: if ciu_drive and ciu_sample are

  specified in clock-names, should contain handles to these clocks.



* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt

  two more clocks "ciu-drive" and "ciu-sample" are supported. They are used

  to control the clock phases, "ciu-sample" is required for tuning high-

  speed modes.



* rockchip,default-sample-phase: The default phase to set ciu_sample at

  probing, low speeds or in case where all phases work at tuning time.

  If not specified 0 deg will be used.



Example:



	rkdwmmc0@12200000 {