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Commit 174f1a71 authored by Alexandre Bounine's avatar Alexandre Bounine Committed by Linus Torvalds
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rapidio/tsi721: fix hardcoded MRRS setting 



Remove use of hardcoded setting for Maximum Read Request Size (MRRS)
value and use one set by PCIe bus driver.

Using hardcoded value can cause PCIe bus errors on platforms that have
tsi721 device on PCIe path that allows only smaller read request sizes.

This fix is applicable to kernel versions starting from v3.2.

Signed-off-by: default avatarAlexandre Bounine <alexandre.bounine@idt.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
Cc: Andre van Herk <andre.van.herk@prodrive-technologies.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 92444bb3

drivers/rapidio/devices/tsi721.c

+2 −4
Original line number Diff line number Diff line
@@ -2426,11 +2426,9 @@ static int tsi721_probe(struct pci_dev *pdev, 


	BUG_ON(!pci_is_pcie(pdev));



	/* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */

	/* Clear "no snoop" and "relaxed ordering" bits. */

	pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,

		PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |

		PCI_EXP_DEVCTL_NOSNOOP_EN,

		PCI_EXP_DEVCTL_READRQ_512B);

		PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN, 0);



	/* Adjust PCIe completion timeout. */

	pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2);