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Commit 174bbb37 authored by Siddhartha Agrawal's avatar Siddhartha Agrawal Committed by Narendra Muppalla
Browse files

clk: msm: mdss: Add support for DSI PLL 1 clock registration 



Setup DSI 1 PLL clock heirarchy. This is needed for instances
where we need to turn off the second pll in case of current
leak issue.

Change-Id: I694af1fa9591b2345709687c9e7b1d69f15b56a9
Signed-off-by: default avatarSiddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent a91de84b

drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c

+111 −59
Original line number Diff line number Diff line
@@ -56,6 +56,20 @@ static int vco_set_rate_20nm(struct clk *c, unsigned long rate) 
	return rc;

}



static int pll1_vco_set_rate_20nm(struct clk *c, unsigned long rate)

{

	struct dsi_pll_vco_clk *vco = to_vco_clk(c);

	struct mdss_pll_resources *pll_res = vco->priv;



	mdss_pll_resource_enable(pll_res, true);

	__dsi_pll_disable(pll_res->pll_base);

	mdss_pll_resource_enable(pll_res, false);



	pr_debug("Configuring PLL1 registers.\n");



	return 0;

}



static int shadow_vco_set_rate_20nm(struct clk *c, unsigned long rate)

{

	int rc;
@@ -111,6 +125,11 @@ static int dsi_pll_enable_seq_8994(struct mdss_pll_resources *dsi_pll_res) 
}



/* Op structures */



static const struct clk_ops pll1_clk_ops_dsi_vco = {

	.set_rate = pll1_vco_set_rate_20nm,

};



static const struct clk_ops clk_ops_dsi_vco = {

	.set_rate = vco_set_rate_20nm,

	.round_rate = pll_20nm_vco_round_rate,
@@ -175,6 +194,15 @@ static struct clk_mux_ops mdss_pixel_mux_ops = { 
	.get_mux_sel = get_mdss_pixel_mux_sel,

};



static struct dsi_pll_vco_clk mdss_dsi1_vco_clk_src = {

	.c = {

		.dbg_name = "mdss_dsi1_vco_clk_src",

		.ops = &pll1_clk_ops_dsi_vco,

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(mdss_dsi1_vco_clk_src.c),

	},

};



static struct dsi_pll_vco_clk dsi_vco_clk_8994 = {

	.ref_clk_rate = 19200000,

	.min_rate = 1000000000,
@@ -435,6 +463,10 @@ static struct mux_clk mdss_byte_clk_mux = { 
	}

};



static struct clk_lookup mdss_dsi_pll_1_cc_8994[] = {

	CLK_LIST(mdss_dsi1_vco_clk_src),

};



static struct clk_lookup mdss_dsi_pllcc_8994[] = {

	CLK_LIST(mdss_pixel_clk_mux),

	CLK_LIST(mdss_byte_clk_mux),
@@ -519,7 +551,12 @@ int dsi_pll_clock_register_20nm(struct platform_device *pdev, 
		return -EPROBE_DEFER;

	}



	/* Set client data to mux, div and vco clocks */

	/*

	 * Set client data to mux, div and vco clocks.

	 * This needs to be done only for PLL0 since, that is the one in

	 * use.

	 **/

	if (!pll_res->index) {

		byte_clk_src.priv = pll_res;

		pixel_clk_src.priv = pll_res;

		bypass_lp_div_mux_8994.priv = pll_res;
@@ -562,18 +599,31 @@ int dsi_pll_clock_register_20nm(struct platform_device *pdev, 


		shadow_byte_clk_src_ops = clk_ops_div;

		shadow_byte_clk_src_ops.prepare = dsi_pll_div_prepare;

	} else {

		mdss_dsi1_vco_clk_src.priv = pll_res;

	}



	if (pll_res->target_id == MDSS_PLL_TARGET_8994) {

		pll_res->gdsc_cb.notifier_call =

			dsi_pll_regulator_notifier_call;

		INIT_WORK(&pll_res->pll_off, dsi_pll_off_work);



		if (pll_res->index) {

			rc = of_msm_clock_register(pdev->dev.of_node,

			mdss_dsi_pllcc_8994, ARRAY_SIZE(mdss_dsi_pllcc_8994));

					mdss_dsi_pll_1_cc_8994,

					ARRAY_SIZE(mdss_dsi_pll_1_cc_8994));

			if (rc) {

				pr_err("Clock register failed\n");

				rc = -EPROBE_DEFER;

			}

		} else {

			rc = of_msm_clock_register(pdev->dev.of_node,

				mdss_dsi_pllcc_8994,

				ARRAY_SIZE(mdss_dsi_pllcc_8994));

			if (rc) {

				pr_err("Clock register failed\n");

				rc = -EPROBE_DEFER;

			}

			pll_res->gdsc_cb.notifier_call =

				dsi_pll_regulator_notifier_call;

			INIT_WORK(&pll_res->pll_off, dsi_pll_off_work);



			pll_reg = mdss_pll_get_mp_by_reg_name(pll_res, "gdsc");

			if (pll_reg) {

				pr_debug("Registering for gdsc regulator events\n");
@@ -581,6 +631,8 @@ int dsi_pll_clock_register_20nm(struct platform_device *pdev, 
							&(pll_res->gdsc_cb)))

					pr_err("Regulator notification registration failed!\n");

			}

		}



	} else {

		pr_err("Invalid target ID\n");

		rc = -EINVAL;

drivers/clk/qcom/mdss/mdss-pll.c

+7 −0
Original line number Diff line number Diff line
@@ -227,6 +227,13 @@ static int mdss_pll_probe(struct platform_device *pdev) 
	}

	platform_set_drvdata(pdev, pll_res);



	rc = of_property_read_u32(pdev->dev.of_node, "cell-index",

			&pll_res->index);

	if (rc) {

		pr_err("Unable to get the cell-index rc=%d\n", rc);

		pll_res->index = 0;

	}



	pll_base_reg = platform_get_resource_byname(pdev,

						IORESOURCE_MEM, "pll_base");

	if (!pll_base_reg) {

drivers/clk/qcom/mdss/mdss-pll.h

+6 −0
Original line number Diff line number Diff line
@@ -119,6 +119,12 @@ struct mdss_pll_resources { 
	 */

	struct work_struct pll_off;



	/*

	 * PLL index if multiple index are available. Eg. in case of

	 * DSI we have 2 plls.

	 */

	uint32_t index;



};



struct mdss_pll_vco_calc {