Commit 16fb7527 authored Dec 14, 2017 by David Collins

clk: qcom: gcc-sdxpoorwills: change halt check for some PCIe clocks



The gcc_pcie_pipe_clk and gcc_pcie_aux_clk clocks are sourced
from external clocks inside of the PCIe PHY.  There is no
guarantee that these clocks are enabled after their parent or
that they are disabled before their parent.

Therefore, change the halt_check for these clocks to
BRANCH_HALT_DELAY so that the clock status bit is not polled
when enabling or disabling the clocks.  Such status checking
leads to unnecessary error logging and error return values.

Change-Id: Idd7f48acdf925056ae8dfc9d2db15c2763e63b4b
Signed-off-by: David Collins <collinsd@codeaurora.org>

parent 21a1b0f4

drivers/clk/qcom/gcc-sdxpoorwills.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1368,7 +1368,7 @@ static struct clk_branch gcc_pcie_0_clkref_clk = {

		static struct clk_branch gcc_pcie_aux_clk = {
		.halt_reg = 0x37020,
		.halt_check = BRANCH_HALT_VOTED,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x6d00c,
		.enable_mask = BIT(3),
		@@ -1427,7 +1427,7 @@ static struct clk_branch gcc_pcie_phy_refgen_clk = {

		static struct clk_branch gcc_pcie_pipe_clk = {
		.halt_reg = 0x37028,
		.halt_check = BRANCH_HALT_VOTED,
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x6d00c,
		.enable_mask = BIT(4),