Merge "clk: qcom: Remove control of the QM clocks from APPS on SDM845" into msm-4.9 (160f20d3) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/gcc-sdm845.c

+0 −60

Original line number	Diff line number	Diff line
		@@ -328,32 +328,6 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
		},
		};

		static const struct freq_tbl ftbl_gcc_mmss_qm_core_clk_src[] = {
		F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
		F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
		F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
		{ }
		};

		static struct clk_rcg2 gcc_mmss_qm_core_clk_src = {
		.cmd_rcgr = 0xb040,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_mmss_qm_core_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_mmss_qm_core_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		VDD_CX_FMAX_MAP3(
		MIN, 75000000,
		LOWER, 150000000,
		LOW, 300000000),
		},
		};

		static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
		F(9600000, P_BI_TCXO, 2, 0, 0),
		F(19200000, P_BI_TCXO, 1, 0, 0),
		@@ -1669,37 +1643,6 @@ static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
		},
		};

		static struct clk_branch gcc_mmss_qm_ahb_clk = {
		.halt_reg = 0xb05c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0xb05c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mmss_qm_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mmss_qm_core_clk = {
		.halt_reg = 0xb038,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0xb038,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mmss_qm_core_clk",
		.parent_names = (const char *[]){
		"gcc_mmss_qm_core_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_axis2_clk = {
		.halt_reg = 0x8a008,
		.halt_check = BRANCH_HALT,
		@@ -3233,9 +3176,6 @@ static struct clk_regmap *gcc_sdm845_clocks[] = {
		[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
		[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
		[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
		[GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
		[GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
		[GCC_MMSS_QM_CORE_CLK_SRC] = &gcc_mmss_qm_core_clk_src.clkr,
		[GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
		[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
		[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,

include/dt-bindings/clock/qcom,gcc-sdm845.h

+143 −146

Original line number	Diff line number	Diff line
		@@ -53,152 +53,149 @@
		#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
		#define GCC_GPU_MEMNOC_GFX_CLK 36
		#define GCC_GPU_SNOC_DVM_GFX_CLK 37
		#define GCC_MMSS_QM_AHB_CLK 38
		#define GCC_MMSS_QM_CORE_CLK 39
		#define GCC_MMSS_QM_CORE_CLK_SRC 40
		#define GCC_MSS_AXIS2_CLK 41
		#define GCC_MSS_CFG_AHB_CLK 42
		#define GCC_MSS_GPLL0_DIV_CLK_SRC 43
		#define GCC_MSS_MFAB_AXIS_CLK 44
		#define GCC_MSS_Q6_MEMNOC_AXI_CLK 45
		#define GCC_MSS_SNOC_AXI_CLK 46
		#define GCC_PCIE_0_AUX_CLK 47
		#define GCC_PCIE_0_AUX_CLK_SRC 48
		#define GCC_PCIE_0_CFG_AHB_CLK 49
		#define GCC_PCIE_0_CLKREF_CLK 50
		#define GCC_PCIE_0_MSTR_AXI_CLK 51
		#define GCC_PCIE_0_PIPE_CLK 52
		#define GCC_PCIE_0_SLV_AXI_CLK 53
		#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 54
		#define GCC_PCIE_1_AUX_CLK 55
		#define GCC_PCIE_1_AUX_CLK_SRC 56
		#define GCC_PCIE_1_CFG_AHB_CLK 57
		#define GCC_PCIE_1_CLKREF_CLK 58
		#define GCC_PCIE_1_MSTR_AXI_CLK 59
		#define GCC_PCIE_1_PIPE_CLK 60
		#define GCC_PCIE_1_SLV_AXI_CLK 61
		#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62
		#define GCC_PCIE_PHY_AUX_CLK 63
		#define GCC_PCIE_PHY_REFGEN_CLK 64
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 65
		#define GCC_PDM2_CLK 66
		#define GCC_PDM2_CLK_SRC 67
		#define GCC_PDM_AHB_CLK 68
		#define GCC_PDM_XO4_CLK 69
		#define GCC_PRNG_AHB_CLK 70
		#define GCC_QMIP_CAMERA_AHB_CLK 71
		#define GCC_QMIP_DISP_AHB_CLK 72
		#define GCC_QMIP_VIDEO_AHB_CLK 73
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 74
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK_SRC 75
		#define GCC_QUPV3_WRAP0_CORE_CLK 76
		#define GCC_QUPV3_WRAP0_S0_CLK 77
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 78
		#define GCC_QUPV3_WRAP0_S1_CLK 79
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 80
		#define GCC_QUPV3_WRAP0_S2_CLK 81
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 82
		#define GCC_QUPV3_WRAP0_S3_CLK 83
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 84
		#define GCC_QUPV3_WRAP0_S4_CLK 85
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 86
		#define GCC_QUPV3_WRAP0_S5_CLK 87
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 88
		#define GCC_QUPV3_WRAP0_S6_CLK 89
		#define GCC_QUPV3_WRAP0_S6_CLK_SRC 90
		#define GCC_QUPV3_WRAP0_S7_CLK 91
		#define GCC_QUPV3_WRAP0_S7_CLK_SRC 92
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93
		#define GCC_QUPV3_WRAP1_CORE_CLK 94
		#define GCC_QUPV3_WRAP1_S0_CLK 95
		#define GCC_QUPV3_WRAP1_S0_CLK_SRC 96
		#define GCC_QUPV3_WRAP1_S1_CLK 97
		#define GCC_QUPV3_WRAP1_S1_CLK_SRC 98
		#define GCC_QUPV3_WRAP1_S2_CLK 99
		#define GCC_QUPV3_WRAP1_S2_CLK_SRC 100
		#define GCC_QUPV3_WRAP1_S3_CLK 101
		#define GCC_QUPV3_WRAP1_S3_CLK_SRC 102
		#define GCC_QUPV3_WRAP1_S4_CLK 103
		#define GCC_QUPV3_WRAP1_S4_CLK_SRC 104
		#define GCC_QUPV3_WRAP1_S5_CLK 105
		#define GCC_QUPV3_WRAP1_S5_CLK_SRC 106
		#define GCC_QUPV3_WRAP1_S6_CLK 107
		#define GCC_QUPV3_WRAP1_S6_CLK_SRC 108
		#define GCC_QUPV3_WRAP1_S7_CLK 109
		#define GCC_QUPV3_WRAP1_S7_CLK_SRC 110
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 111
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 112
		#define GCC_QUPV3_WRAP_1_M_AHB_CLK 113
		#define GCC_QUPV3_WRAP_1_S_AHB_CLK 114
		#define GCC_RX1_USB2_CLKREF_CLK 115
		#define GCC_RX2_QLINK_CLKREF_CLK 116
		#define GCC_RX3_MODEM_CLKREF_CLK 117
		#define GCC_SDCC2_AHB_CLK 118
		#define GCC_SDCC2_APPS_CLK 119
		#define GCC_SDCC2_APPS_CLK_SRC 120
		#define GCC_SDCC4_AHB_CLK 121
		#define GCC_SDCC4_APPS_CLK 122
		#define GCC_SDCC4_APPS_CLK_SRC 123
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 124
		#define GCC_TSIF_AHB_CLK 125
		#define GCC_TSIF_INACTIVITY_TIMERS_CLK 126
		#define GCC_TSIF_REF_CLK 127
		#define GCC_TSIF_REF_CLK_SRC 128
		#define GCC_UFS_CARD_AHB_CLK 129
		#define GCC_UFS_CARD_AXI_CLK 130
		#define GCC_UFS_CARD_AXI_CLK_SRC 131
		#define GCC_UFS_CARD_CLKREF_CLK 132
		#define GCC_UFS_CARD_ICE_CORE_CLK 133
		#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 134
		#define GCC_UFS_CARD_PHY_AUX_CLK 135
		#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 136
		#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 137
		#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 138
		#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 139
		#define GCC_UFS_CARD_UNIPRO_CORE_CLK 140
		#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 141
		#define GCC_UFS_MEM_CLKREF_CLK 142
		#define GCC_UFS_PHY_AHB_CLK 143
		#define GCC_UFS_PHY_AXI_CLK 144
		#define GCC_UFS_PHY_AXI_CLK_SRC 145
		#define GCC_UFS_PHY_ICE_CORE_CLK 146
		#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 147
		#define GCC_UFS_PHY_PHY_AUX_CLK 148
		#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 149
		#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 150
		#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 151
		#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 152
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK 153
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 154
		#define GCC_USB30_PRIM_MASTER_CLK 155
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 156
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 157
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 158
		#define GCC_USB30_PRIM_SLEEP_CLK 159
		#define GCC_USB30_SEC_MASTER_CLK 160
		#define GCC_USB30_SEC_MASTER_CLK_SRC 161
		#define GCC_USB30_SEC_MOCK_UTMI_CLK 162
		#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 163
		#define GCC_USB30_SEC_SLEEP_CLK 164
		#define GCC_USB3_PRIM_CLKREF_CLK 165
		#define GCC_USB3_PRIM_PHY_AUX_CLK 166
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 167
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 168
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 169
		#define GCC_USB3_SEC_CLKREF_CLK 170
		#define GCC_USB3_SEC_PHY_AUX_CLK 171
		#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 172
		#define GCC_USB3_SEC_PHY_COM_AUX_CLK 173
		#define GCC_USB3_SEC_PHY_PIPE_CLK 174
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 175
		#define GCC_VIDEO_AHB_CLK 176
		#define GCC_VIDEO_AXI_CLK 177
		#define GCC_VIDEO_XO_CLK 178
		#define GPLL0 179
		#define GPLL0_OUT_EVEN 180
		#define GPLL0_OUT_MAIN 181
		#define GPLL1 182
		#define GPLL1_OUT_MAIN 183
		#define GCC_MSS_AXIS2_CLK 38
		#define GCC_MSS_CFG_AHB_CLK 39
		#define GCC_MSS_GPLL0_DIV_CLK_SRC 40
		#define GCC_MSS_MFAB_AXIS_CLK 41
		#define GCC_MSS_Q6_MEMNOC_AXI_CLK 42
		#define GCC_MSS_SNOC_AXI_CLK 43
		#define GCC_PCIE_0_AUX_CLK 44
		#define GCC_PCIE_0_AUX_CLK_SRC 45
		#define GCC_PCIE_0_CFG_AHB_CLK 46
		#define GCC_PCIE_0_CLKREF_CLK 47
		#define GCC_PCIE_0_MSTR_AXI_CLK 48
		#define GCC_PCIE_0_PIPE_CLK 49
		#define GCC_PCIE_0_SLV_AXI_CLK 50
		#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 51
		#define GCC_PCIE_1_AUX_CLK 52
		#define GCC_PCIE_1_AUX_CLK_SRC 53
		#define GCC_PCIE_1_CFG_AHB_CLK 54
		#define GCC_PCIE_1_CLKREF_CLK 55
		#define GCC_PCIE_1_MSTR_AXI_CLK 56
		#define GCC_PCIE_1_PIPE_CLK 57
		#define GCC_PCIE_1_SLV_AXI_CLK 58
		#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 59
		#define GCC_PCIE_PHY_AUX_CLK 60
		#define GCC_PCIE_PHY_REFGEN_CLK 61
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 62
		#define GCC_PDM2_CLK 63
		#define GCC_PDM2_CLK_SRC 64
		#define GCC_PDM_AHB_CLK 65
		#define GCC_PDM_XO4_CLK 66
		#define GCC_PRNG_AHB_CLK 67
		#define GCC_QMIP_CAMERA_AHB_CLK 68
		#define GCC_QMIP_DISP_AHB_CLK 69
		#define GCC_QMIP_VIDEO_AHB_CLK 70
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 71
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK_SRC 72
		#define GCC_QUPV3_WRAP0_CORE_CLK 73
		#define GCC_QUPV3_WRAP0_S0_CLK 74
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 75
		#define GCC_QUPV3_WRAP0_S1_CLK 76
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 77
		#define GCC_QUPV3_WRAP0_S2_CLK 78
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 79
		#define GCC_QUPV3_WRAP0_S3_CLK 80
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 81
		#define GCC_QUPV3_WRAP0_S4_CLK 82
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 83
		#define GCC_QUPV3_WRAP0_S5_CLK 84
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 85
		#define GCC_QUPV3_WRAP0_S6_CLK 86
		#define GCC_QUPV3_WRAP0_S6_CLK_SRC 87
		#define GCC_QUPV3_WRAP0_S7_CLK 88
		#define GCC_QUPV3_WRAP0_S7_CLK_SRC 89
		#define GCC_QUPV3_WRAP1_CORE_2X_CLK 90
		#define GCC_QUPV3_WRAP1_CORE_CLK 91
		#define GCC_QUPV3_WRAP1_S0_CLK 92
		#define GCC_QUPV3_WRAP1_S0_CLK_SRC 93
		#define GCC_QUPV3_WRAP1_S1_CLK 94
		#define GCC_QUPV3_WRAP1_S1_CLK_SRC 95
		#define GCC_QUPV3_WRAP1_S2_CLK 96
		#define GCC_QUPV3_WRAP1_S2_CLK_SRC 97
		#define GCC_QUPV3_WRAP1_S3_CLK 98
		#define GCC_QUPV3_WRAP1_S3_CLK_SRC 99
		#define GCC_QUPV3_WRAP1_S4_CLK 100
		#define GCC_QUPV3_WRAP1_S4_CLK_SRC 101
		#define GCC_QUPV3_WRAP1_S5_CLK 102
		#define GCC_QUPV3_WRAP1_S5_CLK_SRC 103
		#define GCC_QUPV3_WRAP1_S6_CLK 104
		#define GCC_QUPV3_WRAP1_S6_CLK_SRC 105
		#define GCC_QUPV3_WRAP1_S7_CLK 106
		#define GCC_QUPV3_WRAP1_S7_CLK_SRC 107
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 108
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 109
		#define GCC_QUPV3_WRAP_1_M_AHB_CLK 110
		#define GCC_QUPV3_WRAP_1_S_AHB_CLK 111
		#define GCC_RX1_USB2_CLKREF_CLK 112
		#define GCC_RX2_QLINK_CLKREF_CLK 113
		#define GCC_RX3_MODEM_CLKREF_CLK 114
		#define GCC_SDCC2_AHB_CLK 115
		#define GCC_SDCC2_APPS_CLK 116
		#define GCC_SDCC2_APPS_CLK_SRC 117
		#define GCC_SDCC4_AHB_CLK 118
		#define GCC_SDCC4_APPS_CLK 119
		#define GCC_SDCC4_APPS_CLK_SRC 120
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 121
		#define GCC_TSIF_AHB_CLK 122
		#define GCC_TSIF_INACTIVITY_TIMERS_CLK 123
		#define GCC_TSIF_REF_CLK 124
		#define GCC_TSIF_REF_CLK_SRC 125
		#define GCC_UFS_CARD_AHB_CLK 126
		#define GCC_UFS_CARD_AXI_CLK 127
		#define GCC_UFS_CARD_AXI_CLK_SRC 128
		#define GCC_UFS_CARD_CLKREF_CLK 129
		#define GCC_UFS_CARD_ICE_CORE_CLK 130
		#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 131
		#define GCC_UFS_CARD_PHY_AUX_CLK 132
		#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 133
		#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 134
		#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 135
		#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 136
		#define GCC_UFS_CARD_UNIPRO_CORE_CLK 137
		#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 138
		#define GCC_UFS_MEM_CLKREF_CLK 139
		#define GCC_UFS_PHY_AHB_CLK 140
		#define GCC_UFS_PHY_AXI_CLK 141
		#define GCC_UFS_PHY_AXI_CLK_SRC 142
		#define GCC_UFS_PHY_ICE_CORE_CLK 143
		#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 144
		#define GCC_UFS_PHY_PHY_AUX_CLK 145
		#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 146
		#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 147
		#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 148
		#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 149
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK 150
		#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 151
		#define GCC_USB30_PRIM_MASTER_CLK 152
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 153
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 154
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 155
		#define GCC_USB30_PRIM_SLEEP_CLK 156
		#define GCC_USB30_SEC_MASTER_CLK 157
		#define GCC_USB30_SEC_MASTER_CLK_SRC 158
		#define GCC_USB30_SEC_MOCK_UTMI_CLK 159
		#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 160
		#define GCC_USB30_SEC_SLEEP_CLK 161
		#define GCC_USB3_PRIM_CLKREF_CLK 162
		#define GCC_USB3_PRIM_PHY_AUX_CLK 163
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 164
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 165
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 166
		#define GCC_USB3_SEC_CLKREF_CLK 167
		#define GCC_USB3_SEC_PHY_AUX_CLK 168
		#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 169
		#define GCC_USB3_SEC_PHY_COM_AUX_CLK 170
		#define GCC_USB3_SEC_PHY_PIPE_CLK 171
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 172
		#define GCC_VIDEO_AHB_CLK 173
		#define GCC_VIDEO_AXI_CLK 174
		#define GCC_VIDEO_XO_CLK 175
		#define GPLL0 176
		#define GPLL0_OUT_EVEN 177
		#define GPLL0_OUT_MAIN 178
		#define GPLL1 179
		#define GPLL1_OUT_MAIN 180

		/* GCC reset clocks */
		#define GCC_GPU_BCR 0