Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 15e9aca8 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: gcc-sdm845: Add reset clock registers for USB on SDM845 



Add the missing USB BCR register modelling on SDM845.

Change-Id: I2dd245468f144cec6e28efd51de25a6fc490110c
CRs-Fixed: 2019404
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 4cc5e34d

drivers/clk/qcom/gcc-sdm845.c

+8 −0
Original line number Diff line number Diff line
@@ -3404,6 +3404,8 @@ static const struct qcom_reset_map gcc_sdm845_resets[] = { 
	[GCC_PRNG_BCR] = { 0x34000 },

	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },

	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },

	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },

	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },

	[GCC_SDCC2_BCR] = { 0x14000 },

	[GCC_SDCC4_BCR] = { 0x16000 },

	[GCC_TSIF_BCR] = { 0x36000 },
@@ -3411,6 +3413,12 @@ static const struct qcom_reset_map gcc_sdm845_resets[] = { 
	[GCC_UFS_PHY_BCR] = { 0x77000 },

	[GCC_USB30_PRIM_BCR] = { 0xf000 },

	[GCC_USB30_SEC_BCR] = { 0x10000 },

	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },

	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },

	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },

	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },

	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },

	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },

	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },

};

include/dt-bindings/clock/qcom,gcc-sdm845.h

+17 −9
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -219,13 +219,21 @@ 
#define GCC_PRNG_BCR						6

#define GCC_QUPV3_WRAPPER_0_BCR					7

#define GCC_QUPV3_WRAPPER_1_BCR					8

#define GCC_SDCC2_BCR						9

#define GCC_SDCC4_BCR						10

#define GCC_TSIF_BCR						11

#define GCC_UFS_CARD_BCR					12

#define GCC_UFS_PHY_BCR						13

#define GCC_USB30_PRIM_BCR					14

#define GCC_USB30_SEC_BCR					15

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				16

#define GCC_QUSB2PHY_PRIM_BCR					9

#define GCC_QUSB2PHY_SEC_BCR					10

#define GCC_SDCC2_BCR						11

#define GCC_SDCC4_BCR						12

#define GCC_TSIF_BCR						13

#define GCC_UFS_CARD_BCR					14

#define GCC_UFS_PHY_BCR						15

#define GCC_USB30_PRIM_BCR					16

#define GCC_USB30_SEC_BCR					17

#define GCC_USB3_PHY_PRIM_BCR					18

#define GCC_USB3PHY_PHY_PRIM_BCR				19

#define GCC_USB3_DP_PHY_PRIM_BCR				20

#define GCC_USB3_PHY_SEC_BCR					21

#define GCC_USB3PHY_PHY_SEC_BCR					22

#define GCC_USB3_DP_PHY_SEC_BCR					23

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				24



#endif