drm/i915: Move pll power state to crtc power domains. (15e7ec29) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/i915/intel_display.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -5273,6 +5273,9 @@ static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
		mask \|= BIT(intel_display_port_power_domain(intel_encoder));
		}

		if (crtc_state->shared_dpll)
		mask \|= BIT(POWER_DOMAIN_PLLS);

		return mask;
		}

		@@ -15703,9 +15706,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)

		DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
		pll->name, pll->config.crtc_mask, pll->on);

		if (pll->config.crtc_mask)
		intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
		}

		for_each_intel_encoder(dev, encoder) {

+0 −4

Original line number	Diff line number	Diff line
		@@ -135,8 +135,6 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
		}
		WARN_ON(pll->on);

		intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);

		DRM_DEBUG_KMS("enabling %s\n", pll->name);
		pll->funcs.enable(dev_priv, pll);
		pll->on = true;
		@@ -173,8 +171,6 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
		DRM_DEBUG_KMS("disabling %s\n", pll->name);
		pll->funcs.disable(dev_priv, pll);
		pll->on = false;

		intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
		}

		static struct intel_shared_dpll *