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Commit 15d07dc9 authored by Russell King's avatar Russell King Committed by David Howells
Browse files

ARM: move CP15 definitions to separate header file 



Avoid namespace conflicts with drivers over the CP15 definitions by
moving CP15 related prototypes and definitions to a private header
file.

Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com> [Tegra]
Acked-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> [EP93xx]
Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
parent ec221208

arch/arm/include/asm/cp15.h

0 → 100644
+87 −0
Original line number Diff line number Diff line 
#ifndef __ASM_ARM_CP15_H

#define __ASM_ARM_CP15_H



#include <asm/system.h>



/*

 * CR1 bits (CP#15 CR1)

 */

#define CR_M	(1 << 0)	/* MMU enable				*/

#define CR_A	(1 << 1)	/* Alignment abort enable		*/

#define CR_C	(1 << 2)	/* Dcache enable			*/

#define CR_W	(1 << 3)	/* Write buffer enable			*/

#define CR_P	(1 << 4)	/* 32-bit exception handler		*/

#define CR_D	(1 << 5)	/* 32-bit data address range		*/

#define CR_L	(1 << 6)	/* Implementation defined		*/

#define CR_B	(1 << 7)	/* Big endian				*/

#define CR_S	(1 << 8)	/* System MMU protection		*/

#define CR_R	(1 << 9)	/* ROM MMU protection			*/

#define CR_F	(1 << 10)	/* Implementation defined		*/

#define CR_Z	(1 << 11)	/* Implementation defined		*/

#define CR_I	(1 << 12)	/* Icache enable			*/

#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/

#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/

#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/

#define CR_DT	(1 << 16)

#define CR_IT	(1 << 18)

#define CR_ST	(1 << 19)

#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/

#define CR_U	(1 << 22)	/* Unaligned access operation		*/

#define CR_XP	(1 << 23)	/* Extended page tables			*/

#define CR_VE	(1 << 24)	/* Vectored interrupts			*/

#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/

#define CR_TRE	(1 << 28)	/* TEX remap enable			*/

#define CR_AFE	(1 << 29)	/* Access flag enable			*/

#define CR_TE	(1 << 30)	/* Thumb exception enable		*/



#ifndef __ASSEMBLY__



#if __LINUX_ARM_ARCH__ >= 4

#define vectors_high()	(cr_alignment & CR_V)

#else

#define vectors_high()	(0)

#endif



extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */

extern unsigned long cr_alignment;	/* defined in entry-armv.S */



static inline unsigned int get_cr(void)

{

	unsigned int val;

	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");

	return val;

}



static inline void set_cr(unsigned int val)

{

	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"

	  : : "r" (val) : "cc");

	isb();

}



#ifndef CONFIG_SMP

extern void adjust_cr(unsigned long mask, unsigned long set);

#endif



#define CPACC_FULL(n)		(3 << (n * 2))

#define CPACC_SVC(n)		(1 << (n * 2))

#define CPACC_DISABLE(n)	(0 << (n * 2))



static inline unsigned int get_copro_access(void)

{

	unsigned int val;

	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"

	  : "=r" (val) : : "cc");

	return val;

}



static inline void set_copro_access(unsigned int val)

{

	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"

	  : : "r" (val) : "cc");

	isb();

}



#endif



#endif

arch/arm/include/asm/system.h

+0 −77
Original line number Diff line number Diff line
@@ -14,37 +14,6 @@ 
#define CPU_ARCH_ARMv6		8

#define CPU_ARCH_ARMv7		9



/*

 * CR1 bits (CP#15 CR1)

 */

#define CR_M	(1 << 0)	/* MMU enable				*/

#define CR_A	(1 << 1)	/* Alignment abort enable		*/

#define CR_C	(1 << 2)	/* Dcache enable			*/

#define CR_W	(1 << 3)	/* Write buffer enable			*/

#define CR_P	(1 << 4)	/* 32-bit exception handler		*/

#define CR_D	(1 << 5)	/* 32-bit data address range		*/

#define CR_L	(1 << 6)	/* Implementation defined		*/

#define CR_B	(1 << 7)	/* Big endian				*/

#define CR_S	(1 << 8)	/* System MMU protection		*/

#define CR_R	(1 << 9)	/* ROM MMU protection			*/

#define CR_F	(1 << 10)	/* Implementation defined		*/

#define CR_Z	(1 << 11)	/* Implementation defined		*/

#define CR_I	(1 << 12)	/* Icache enable			*/

#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/

#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/

#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/

#define CR_DT	(1 << 16)

#define CR_IT	(1 << 18)

#define CR_ST	(1 << 19)

#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/

#define CR_U	(1 << 22)	/* Unaligned access operation		*/

#define CR_XP	(1 << 23)	/* Extended page tables			*/

#define CR_VE	(1 << 24)	/* Vectored interrupts			*/

#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/

#define CR_TRE	(1 << 28)	/* TEX remap enable			*/

#define CR_AFE	(1 << 29)	/* Access flag enable			*/

#define CR_TE	(1 << 30)	/* Thumb exception enable		*/



/*

 * This is used to ensure the compiler did actually allocate the register we

 * asked it for some inline assembly sequences.  Apparently we can't trust
@@ -119,12 +88,6 @@ extern void (*arm_pm_restart)(char str, const char *cmd); 


extern unsigned int user_debug;



#if __LINUX_ARM_ARCH__ >= 4

#define vectors_high()	(cr_alignment & CR_V)

#else

#define vectors_high()	(0)

#endif



#if __LINUX_ARM_ARCH__ >= 7 ||		\

	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))

#define sev()	__asm__ __volatile__ ("sev" : : : "memory")
@@ -185,46 +148,6 @@ extern unsigned int user_debug; 
#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)

#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");



extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */

extern unsigned long cr_alignment;	/* defined in entry-armv.S */



static inline unsigned int get_cr(void)

{

	unsigned int val;

	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");

	return val;

}



static inline void set_cr(unsigned int val)

{

	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"

	  : : "r" (val) : "cc");

	isb();

}



#ifndef CONFIG_SMP

extern void adjust_cr(unsigned long mask, unsigned long set);

#endif



#define CPACC_FULL(n)		(3 << (n * 2))

#define CPACC_SVC(n)		(1 << (n * 2))

#define CPACC_DISABLE(n)	(0 << (n * 2))



static inline unsigned int get_copro_access(void)

{

	unsigned int val;

	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"

	  : "=r" (val) : : "cc");

	return val;

}



static inline void set_copro_access(unsigned int val)

{

	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"

	  : : "r" (val) : "cc");

	isb();

}



/*

 * switch_mm() may do a full cache flush over the context switch,

 * so enable interrupts over the context switch to avoid high

arch/arm/kernel/fiq.c

+1 −1
Original line number Diff line number Diff line
@@ -42,9 +42,9 @@ 
#include <linux/seq_file.h>



#include <asm/cacheflush.h>

#include <asm/cp15.h>

#include <asm/fiq.h>

#include <asm/irq.h>

#include <asm/system.h>

#include <asm/traps.h>



static unsigned long no_fiq_insn;

arch/arm/kernel/head-nommu.S

+1 −1
Original line number Diff line number Diff line
@@ -17,8 +17,8 @@ 
#include <asm/assembler.h>

#include <asm/ptrace.h>

#include <asm/asm-offsets.h>

#include <asm/cp15.h>

#include <asm/thread_info.h>

#include <asm/system.h>



/*

 * Kernel startup entry point.

arch/arm/kernel/head.S

+1 −1
Original line number Diff line number Diff line
@@ -15,12 +15,12 @@ 
#include <linux/init.h>



#include <asm/assembler.h>

#include <asm/cp15.h>

#include <asm/domain.h>

#include <asm/ptrace.h>

#include <asm/asm-offsets.h>

#include <asm/memory.h>

#include <asm/thread_info.h>

#include <asm/system.h>

#include <asm/pgtable.h>



#ifdef CONFIG_DEBUG_LL