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Commit 1586505a authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: fix up audio dto programming for DCE2 



Uses a different register than DCE3 asics.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 46892caa

drivers/gpu/drm/radeon/r600_hdmi.c

+12 −3
Original line number Diff line number Diff line
@@ -246,9 +246,18 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) 
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE

	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator

	 */

	WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);

	WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);

	if (ASIC_IS_DCE3(rdev)) {

		/* according to the reg specs, this should DCE3.2 only, but in

		 * practice it seems to cover DCE3.0 as well.

		 */

		WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50);

		WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);

		WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */

	} else {

		/* according to the reg specs, this should be DCE2.0 and DCE3.0 */

		WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) |

		       AUDIO_DTO_MODULE(clock * 100));

	}

}



/*

drivers/gpu/drm/radeon/r600d.h

+6 −1
Original line number Diff line number Diff line
@@ -910,7 +910,12 @@ 
#       define TARGET_LINK_SPEED_MASK                     (0xf << 0)

#       define SELECTABLE_DEEMPHASIS                      (1 << 6)



/* Audio clocks */

/* Audio clocks DCE 2.0/3.0 */

#define AUDIO_DTO                         0x7340

#       define AUDIO_DTO_PHASE(x)         (((x) & 0xffff) << 0)

#       define AUDIO_DTO_MODULE(x)        (((x) & 0xffff) << 16)



/* Audio clocks DCE 3.2 */

#define DCCG_AUDIO_DTO0_PHASE             0x0514

#define DCCG_AUDIO_DTO0_MODULE            0x0518

#define DCCG_AUDIO_DTO0_LOAD              0x051c