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Commit 1559074f authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

ARM: dts: msm: Update speed bin tables for the 3 CPUCC domains on SDM845 



Frequencies above 600 MHz do not need a post-divider. Update
the speed bin configurations for all three CPU clock domains
to correct this.

Change-Id: Ia8e215a5467b10eb9b4966cf9018897476c483a7
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent fd8f40e6

arch/arm64/boot/dts/qcom/sdm845.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -832,17 +832,17 @@ 
			<   422400000 0x50140116 0x00002020 0x1 2 >,

			<   499200000 0x5014021a 0x00002020 0x1 3 >,

			<   576000000 0x5014031e 0x00002020 0x1 4 >,

			<   652800000 0x501c0422 0x00002020 0x1 5 >,

			<   729600000 0x501c0526 0x00002020 0x1 6 >,

			<   806400000 0x501c062a 0x00002222 0x1 7 >;

			<   652800000 0x401c0422 0x00002020 0x1 5 >,

			<   729600000 0x401c0526 0x00002020 0x1 6 >,

			<   806400000 0x401c062a 0x00002222 0x1 7 >;



		qcom,pwrcl-speedbin0-v0 =

			<   300000000 0x000c000f 0x00002020 0x1 1 >,

			<   422400000 0x50140116 0x00002020 0x1 2 >,

			<   499200000 0x5014021a 0x00002020 0x1 3 >,

			<   576000000 0x5014031e 0x00002020 0x1 4 >,

			<   652800000 0x501c0422 0x00002020 0x1 5 >,

			<   748800000 0x501c0527 0x00002020 0x1 6 >,

			<   652800000 0x401c0422 0x00002020 0x1 5 >,

			<   748800000 0x401c0527 0x00002020 0x1 6 >,

			<   825600000 0x401c062b 0x00002222 0x1 7 >,

			<   902400000 0x4024072f 0x00002626 0x1 8 >,

			<   979200000 0x40240833 0x00002929 0x1 9 >,
@@ -855,9 +855,9 @@ 
			<   422400000 0x50140116 0x00002020 0x1 2 >,

			<   499200000 0x5014021a 0x00002020 0x1 3 >,

			<   576000000 0x5014031e 0x00002020 0x1 4 >,

			<   652800000 0x501c0422 0x00002020 0x1 5 >,

			<   729600000 0x501c0526 0x00002020 0x1 6 >,

			<   806400000 0x501c062a 0x00002222 0x1 7 >,

			<   652800000 0x401c0422 0x00002020 0x1 5 >,

			<   729600000 0x401c0526 0x00002020 0x1 6 >,

			<   806400000 0x401c062a 0x00002222 0x1 7 >,

			<   883200000 0x4024072b 0x00002525 0x1 8 >,

			<   960000000 0x40240832 0x00002828 0x1 9 >,

			<  1036800000 0x40240936 0x00002b2b 0x1 10 >,