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Commit 1555b33d authored by Kenji Kaneshige's avatar Kenji Kaneshige Committed by Greg Kroah-Hartman
Browse files

shpchp: remove DBG_XXX_ROUTINE 



This patch removes DBG_ENTER_ROUTINE, DBG_LEAVE_ROUTINE and related
code.

Signed-off-by: default avatarKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: default avatarKristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 3d9c1887

drivers/pci/hotplug/shpchp_hpc.c

+19 −136
Original line number Diff line number Diff line
@@ -35,38 +35,6 @@ 


#include "shpchp.h"



#ifdef DEBUG

#define DBG_K_TRACE_ENTRY      ((unsigned int)0x00000001)	/* On function entry */

#define DBG_K_TRACE_EXIT       ((unsigned int)0x00000002)	/* On function exit */

#define DBG_K_INFO             ((unsigned int)0x00000004)	/* Info messages */

#define DBG_K_ERROR            ((unsigned int)0x00000008)	/* Error messages */

#define DBG_K_TRACE            (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)

#define DBG_K_STANDARD         (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)

/* Redefine this flagword to set debug level */

#define DEBUG_LEVEL            DBG_K_STANDARD



#define DEFINE_DBG_BUFFER     char __dbg_str_buf[256];



#define DBG_PRINT( dbg_flags, args... )              \

	do {                                             \

	  if ( DEBUG_LEVEL & ( dbg_flags ) )             \

	  {                                              \

	    int len;                                     \

	    len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \

		  __FILE__, __LINE__, __FUNCTION__ );    \

	    sprintf( __dbg_str_buf + len, args );        \

	    printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \

	  }                                              \

	} while (0)



#define DBG_ENTER_ROUTINE	DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");

#define DBG_LEAVE_ROUTINE	DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");

#else

#define DEFINE_DBG_BUFFER

#define DBG_ENTER_ROUTINE

#define DBG_LEAVE_ROUTINE

#endif				/* DEBUG */



/* Slot Available Register I field definition */

#define SLOT_33MHZ		0x0000001f

#define SLOT_66MHZ_PCIX		0x00001f00
@@ -211,7 +179,6 @@ 
#define SLOT_EVENT_LATCH	0x2

#define SLOT_SERR_INT_MASK	0x3



DEFINE_DBG_BUFFER		/* Debug string buffer for entire HPC defined here */

static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);



static irqreturn_t shpc_isr(int irq, void *dev_id);
@@ -268,8 +235,6 @@ static void int_poll_timeout(unsigned long data) 
{

	struct controller *ctrl = (struct controller *)data;



	DBG_ENTER_ROUTINE



	/* Poll for interrupt events.  regs == NULL => polling */

	shpc_isr(0, ctrl);
@@ -278,8 +243,6 @@ static void int_poll_timeout(unsigned long data) 
		shpchp_poll_time = 2; /* default polling interval is 2 sec */



	start_int_poll_timer(ctrl, shpchp_poll_time);



	DBG_LEAVE_ROUTINE

}



/*
@@ -353,8 +316,6 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 
	int retval = 0;

	u16 temp_word;



	DBG_ENTER_ROUTINE 



	mutex_lock(&slot->ctrl->cmd_lock);



	if (!shpc_poll_ctrl_busy(ctrl)) {
@@ -389,19 +350,13 @@ static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 
	}

 out:

	mutex_unlock(&slot->ctrl->cmd_lock);



	DBG_LEAVE_ROUTINE 

	return retval;

}



static int hpc_check_cmd_status(struct controller *ctrl)

{

	u16 cmd_status;

	int retval = 0;



	DBG_ENTER_ROUTINE 



	cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;

	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;

	

	switch (cmd_status >> 1) {

	case 0:
@@ -423,7 +378,6 @@ static int hpc_check_cmd_status(struct controller *ctrl) 
		retval = cmd_status;

	}



	DBG_LEAVE_ROUTINE 

	return retval;

}
@@ -431,13 +385,8 @@ static int hpc_check_cmd_status(struct controller *ctrl) 
static int hpc_get_attention_status(struct slot *slot, u8 *status)

{

	struct controller *ctrl = slot->ctrl;

	u32 slot_reg;

	u8 state;

	

	DBG_ENTER_ROUTINE 



	slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));

	state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;

	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));

	u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;



	switch (state) {

	case ATN_LED_STATE_ON:
@@ -454,20 +403,14 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status) 
		break;

	}



	DBG_LEAVE_ROUTINE 

	return 0;

}



static int hpc_get_power_status(struct slot * slot, u8 *status)

{

	struct controller *ctrl = slot->ctrl;

	u32 slot_reg;

	u8 state;

	

	DBG_ENTER_ROUTINE 



	slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));

	state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;

	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));

	u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;



	switch (state) {

	case SLOT_STATE_PWRONLY:
@@ -484,7 +427,6 @@ static int hpc_get_power_status(struct slot * slot, u8 *status) 
		break;

	}



	DBG_LEAVE_ROUTINE 

	return 0;

}
@@ -492,30 +434,21 @@ static int hpc_get_power_status(struct slot * slot, u8 *status) 
static int hpc_get_latch_status(struct slot *slot, u8 *status)

{

	struct controller *ctrl = slot->ctrl;

	u32 slot_reg;



	DBG_ENTER_ROUTINE 

	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));



	slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));

	*status = !!(slot_reg & MRL_SENSOR);	/* 0 -> close; 1 -> open */



	DBG_LEAVE_ROUTINE 

	return 0;

}



static int hpc_get_adapter_status(struct slot *slot, u8 *status)

{

	struct controller *ctrl = slot->ctrl;

	u32 slot_reg;

	u8 state;



	DBG_ENTER_ROUTINE 

	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));

	u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;



	slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));

	state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;

	*status = (state != 0x3) ? 1 : 0;



	DBG_LEAVE_ROUTINE 

	return 0;

}
@@ -523,11 +456,8 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 
{

	struct controller *ctrl = slot->ctrl;



	DBG_ENTER_ROUTINE 



	*prog_int = shpc_readb(ctrl, PROG_INTERFACE);



	DBG_LEAVE_ROUTINE 

	return 0;

}
@@ -539,8 +469,6 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 
	u8 m66_cap  = !!(slot_reg & MHZ66_CAP);

	u8 pi, pcix_cap;



	DBG_ENTER_ROUTINE 



	if ((retval = hpc_get_prog_int(slot, &pi)))

		return retval;
@@ -582,21 +510,15 @@ static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 
	}



	dbg("Adapter speed = %d\n", *value);

	DBG_LEAVE_ROUTINE 

	return retval;

}



static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)

{

	struct controller *ctrl = slot->ctrl;

	u16 sec_bus_status;

	u8 pi;

	int retval = 0;



	DBG_ENTER_ROUTINE 



	pi = shpc_readb(ctrl, PROG_INTERFACE);

	sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);

	struct controller *ctrl = slot->ctrl;

	u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);

	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);



	if (pi == 2) {

		*mode = (sec_bus_status & 0x0100) >> 8;
@@ -605,21 +527,14 @@ static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 
	}



	dbg("Mode 1 ECC cap = %d\n", *mode);

	

	DBG_LEAVE_ROUTINE 

	return retval;

}



static int hpc_query_power_fault(struct slot * slot)

{

	struct controller *ctrl = slot->ctrl;

	u32 slot_reg;



	DBG_ENTER_ROUTINE 



	slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));

	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));



	DBG_LEAVE_ROUTINE

	/* Note: Logic 0 => fault */

	return !(slot_reg & POWER_FAULT);

}
@@ -666,8 +581,6 @@ static void hpc_release_ctlr(struct controller *ctrl) 
	int i;

	u32 slot_reg, serr_int;



	DBG_ENTER_ROUTINE 



	/*

	 * Mask event interrupts and SERRs of all slots

	 */
@@ -708,61 +621,43 @@ static void hpc_release_ctlr(struct controller *ctrl) 
	 */

	if (atomic_dec_and_test(&shpchp_num_controllers))

		destroy_workqueue(shpchp_wq);



	DBG_LEAVE_ROUTINE

}



static int hpc_power_on_slot(struct slot * slot)

{

	int retval;



	DBG_ENTER_ROUTINE 



	retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);

	if (retval) {

	if (retval)

		err("%s: Write command failed!\n", __FUNCTION__);

		return retval;

	}



	DBG_LEAVE_ROUTINE



	return 0;

	return retval;

}



static int hpc_slot_enable(struct slot * slot)

{

	int retval;



	DBG_ENTER_ROUTINE 



	/* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */

	retval = shpc_write_cmd(slot, slot->hp_slot,

			SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);

	if (retval) {

	if (retval)

		err("%s: Write command failed!\n", __FUNCTION__);

		return retval;

	}



	DBG_LEAVE_ROUTINE

	return 0;

	return retval;

}



static int hpc_slot_disable(struct slot * slot)

{

	int retval;



	DBG_ENTER_ROUTINE 



	/* Slot - Disable, Power Indicator - Off, Attention Indicator - On */

	retval = shpc_write_cmd(slot, slot->hp_slot,

			SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);

	if (retval) {

	if (retval)

		err("%s: Write command failed!\n", __FUNCTION__);

		return retval;

	}



	DBG_LEAVE_ROUTINE

	return 0;

	return retval;

}



static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
@@ -771,8 +666,6 @@ static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 
	struct controller *ctrl = slot->ctrl;

	u8 pi, cmd;



	DBG_ENTER_ROUTINE 



	pi = shpc_readb(ctrl, PROG_INTERFACE);

	if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))

		return -EINVAL;
@@ -828,7 +721,6 @@ static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 
	if (retval)

		err("%s: Write command failed!\n", __FUNCTION__);



	DBG_LEAVE_ROUTINE

	return retval;

}
@@ -920,8 +812,6 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) 
	u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);

	u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);



	DBG_ENTER_ROUTINE 



	if (pi == 2) {

		if (slot_avail2 & SLOT_133MHZ_PCIX_533)

			bus_speed = PCI_SPEED_133MHz_PCIX_533;
@@ -954,7 +844,7 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) 


	*value = bus_speed;

	dbg("Max bus speed = %d\n", bus_speed);

	DBG_LEAVE_ROUTINE 



	return retval;

}
@@ -967,8 +857,6 @@ static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) 
	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);

	u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);



	DBG_ENTER_ROUTINE 



	if ((pi == 1) && (speed_mode > 4)) {

		*value = PCI_SPEED_UNKNOWN;

		return -ENODEV;
@@ -1024,7 +912,6 @@ static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) 
	}



	dbg("Current bus speed = %d\n", bus_speed);

	DBG_LEAVE_ROUTINE 

	return retval;

}
@@ -1061,8 +948,6 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 
	u32 tempdword, slot_reg, slot_config;

	u8 i;



	DBG_ENTER_ROUTINE



	ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */



	if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
@@ -1235,13 +1120,11 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 
		dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);

	}



	DBG_LEAVE_ROUTINE

	return 0;



	/* We end up here for the many possible ways to fail this API.  */

abort_iounmap:

	iounmap(ctrl->creg);

abort:

	DBG_LEAVE_ROUTINE

	return rc;

}