Commit 154f66cf authored Jul 01, 2016 by Catalin Marinas Committed by Amit Pundir Oct 24, 2016

FROMLIST: BACKPORT: arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro



This patch takes the errata workaround code out of cpu_do_switch_mm into
a dedicated post_ttbr0_update_workaround macro which will be reused in a
subsequent patch.

Cc: Will Deacon <will.deacon@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Change-Id: I69f94e4c41046bd52ca9340b72d97bfcf955b586
(cherry picked from commit 4398e6a1644373a4c2f535f4153c8378d0914630)
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
[Backport]
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>

parent 7c93e72b

arch/arm64/include/asm/assembler.h

+13 −0

Original line number	Diff line number	Diff line
		@@ -395,4 +395,17 @@ alternative_endif
		movk \reg, :abs_g0_nc:\val
		.endm

		/*
		* Errata workaround post TTBR0_EL1 update.
		*/
		.macro post_ttbr0_update_workaround
		#ifdef CONFIG_CAVIUM_ERRATUM_27456
		alternative_if ARM64_WORKAROUND_CAVIUM_27456
		ic iallu
		dsb nsh
		isb
		alternative_else_nop_endif
		#endif
		.endm

		#endif /* __ASM_ASSEMBLER_H */

arch/arm64/mm/proc.S

+1 −5

Original line number	Diff line number	Diff line
		@@ -136,11 +136,7 @@ ENTRY(cpu_do_switch_mm)
		bfi x0, x1, #48, #16 // set the ASID
		msr ttbr0_el1, x0 // set TTBR0
		isb
		alternative_if ARM64_WORKAROUND_CAVIUM_27456
		ic iallu
		dsb nsh
		isb
		alternative_else_nop_endif
		post_ttbr0_update_workaround
		ret
		ENDPROC(cpu_do_switch_mm)