Loading arch/arm64/boot/dts/qcom/sdm845.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -2127,6 +2127,9 @@ }; &gpu_gx_gdsc { clock-names = "core_root_clk"; clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>; qcom,force-enable-root-clk; parent-supply = <&pm8005_s1_level>; status = "ok"; }; Loading drivers/clk/qcom/gpucc-sdm845.c +1 −1 Original line number Diff line number Diff line Loading @@ -211,9 +211,9 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { .cmd_rcgr = 0x101c, .mnd_width = 0, .hid_width = 5, .enable_safe_config = true, .parent_map = gpu_cc_parent_map_1, .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, .flags = FORCE_ENABLE_RCG, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_gfx3d_clk_src", .parent_names = gpu_cc_parent_names_1, Loading Loading
arch/arm64/boot/dts/qcom/sdm845.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -2127,6 +2127,9 @@ }; &gpu_gx_gdsc { clock-names = "core_root_clk"; clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>; qcom,force-enable-root-clk; parent-supply = <&pm8005_s1_level>; status = "ok"; }; Loading
drivers/clk/qcom/gpucc-sdm845.c +1 −1 Original line number Diff line number Diff line Loading @@ -211,9 +211,9 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { .cmd_rcgr = 0x101c, .mnd_width = 0, .hid_width = 5, .enable_safe_config = true, .parent_map = gpu_cc_parent_map_1, .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, .flags = FORCE_ENABLE_RCG, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_gfx3d_clk_src", .parent_names = gpu_cc_parent_names_1, Loading