Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 14f97d97 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Bunch of fixes all over the place, all pretty small: amdgpu, i915,
  exynos, one qxl and one vmwgfx.

  There is also a bunch of mst fixes, I left some cleanups in the series
  as I didn't think it was worth splitting up the tested series"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (37 commits)
  drm/dp/mst: add some defines for logical/physical ports
  drm/dp/mst: drop cancel work sync in the mstb destroy path (v2)
  drm/dp/mst: split connector registration into two parts (v2)
  drm/dp/mst: update the link_address_sent before sending the link address (v3)
  drm/dp/mst: fixup handling hotplug on port removal.
  drm/dp/mst: don't pass port into the path builder function
  drm/radeon: drop radeon_fb_helper_set_par
  drm: handle cursor_set2 in restore_fbdev_mode
  drm/exynos: Staticize local function in exynos_drm_gem.c
  drm/exynos: fimd: actually disable dp clock
  drm/exynos: dp: remove suspend/resume functions
  drm/qxl: recreate the primary surface when the bo is not primary
  drm/amdgpu: only print meaningful VM faults
  drm/amdgpu/cgs: remove import_gpu_mem
  drm/i915: Call non-locking version of drm_kms_helper_poll_enable(), v2
  drm: Add a non-locking version of drm_kms_helper_poll_enable(), v2
  drm/vmwgfx: Fix a command submission hang regression
  drm/exynos: remove unused mode_fixup() code
  drm/exynos: remove decon_mode_fixup()
  drm/exynos: remove fimd_mode_fixup()
  ...
parents 978ab6a0 ccf03d69

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+0 −39
Original line number Diff line number Diff line
@@ -208,44 +208,6 @@ static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, 
	return ret;

}



static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,

				     cgs_handle_t *handle)

{

	CGS_FUNC_ADEV;

	int r;

	uint32_t dma_handle;

	struct drm_gem_object *obj;

	struct amdgpu_bo *bo;

	struct drm_device *dev = adev->ddev;

	struct drm_file *file_priv = NULL, *priv;



	mutex_lock(&dev->struct_mutex);

	list_for_each_entry(priv, &dev->filelist, lhead) {

		rcu_read_lock();

		if (priv->pid == get_pid(task_pid(current)))

			file_priv = priv;

		rcu_read_unlock();

		if (file_priv)

			break;

	}

	mutex_unlock(&dev->struct_mutex);

	r = dev->driver->prime_fd_to_handle(dev,

					    file_priv, dmabuf_fd,

					    &dma_handle);

	spin_lock(&file_priv->table_lock);



	/* Check if we currently have a reference on the object */

	obj = idr_find(&file_priv->object_idr, dma_handle);

	if (obj == NULL) {

		spin_unlock(&file_priv->table_lock);

		return -EINVAL;

	}

	spin_unlock(&file_priv->table_lock);

	bo = gem_to_amdgpu_bo(obj);

	*handle = (cgs_handle_t)bo;

	return 0;

}



static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)

{

	struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
@@ -810,7 +772,6 @@ static const struct cgs_ops amdgpu_cgs_ops = { 
};



static const struct cgs_os_ops amdgpu_cgs_os_ops = {

	amdgpu_cgs_import_gpu_mem,

	amdgpu_cgs_add_irq_source,

	amdgpu_cgs_irq_get,

	amdgpu_cgs_irq_put

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+2 −1
Original line number Diff line number Diff line
@@ -156,7 +156,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 
	uint64_t *chunk_array_user;

	uint64_t *chunk_array;

	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;

	unsigned size, i;

	unsigned size;

	int i;

	int ret;



	if (cs->in.num_chunks == 0)

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

+1 −2
Original line number Diff line number Diff line
@@ -1279,8 +1279,7 @@ amdgpu_atombios_encoder_setup_dig(struct drm_encoder *encoder, int action) 
			amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);

		}

		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))

			amdgpu_atombios_encoder_setup_dig_transmitter(encoder,

							       ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);

			amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder, dig->backlight_level);

		if (ext_encoder)

			amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_ENABLE);

	} else {

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+6 −2
Original line number Diff line number Diff line
@@ -1262,6 +1262,12 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 
	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);

	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);

	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);

	/* reset addr and status */

	WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);



	if (!addr && !status)

		return 0;



	dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",

		entry->src_id, entry->src_data);

	dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
@@ -1269,8 +1275,6 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 
	dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		status);

	gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);

	/* reset addr and status */

	WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+6 −2
Original line number Diff line number Diff line
@@ -1262,6 +1262,12 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 
	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);

	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);

	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);

	/* reset addr and status */

	WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);



	if (!addr && !status)

		return 0;



	dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",

		entry->src_id, entry->src_data);

	dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
@@ -1269,8 +1275,6 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 
	dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",

		status);

	gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);

	/* reset addr and status */

	WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);



	return 0;

}