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Commit 14a9cbc2 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
Browse files

clk: msm: mdss: handle continuous splash cases in DSI 12nm PLL driver 



Register the DSI 12nm PLL VCO clock with the linux clock driver
for proper handoff of DSI PLL clocks for continuous splash screen during
bootup. For command mode panels, execute the DSI re-lock sequence
during boot-up to enable DSI PLL since DSI PHY is already programmed
in APPS bootloader.

Change-Id: Ieeadfcac2206631d0f278c018a601a5f5fc98727
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent c287f849

drivers/clk/msm/mdss/mdss-dsi-pll-12nm-util.c

+23 −14
Original line number Diff line number Diff line
@@ -165,7 +165,8 @@ int get_gp_mux_sel(struct mux_clk *clk) 
	return sel;

}



static bool pll_is_pll_locked_12nm(struct mdss_pll_resources *pll)

static bool pll_is_pll_locked_12nm(struct mdss_pll_resources *pll,

	bool is_handoff)

{

	u32 status;

	bool pll_locked;
@@ -177,6 +178,7 @@ static bool pll_is_pll_locked_12nm(struct mdss_pll_resources *pll) 
			((status & BIT(1)) > 0),

			DSI_PLL_POLL_MAX_READS,

			DSI_PLL_POLL_TIMEOUT_US)) {

		if (!is_handoff)

			pr_err("DSI PLL ndx=%d status=%x failed to Lock\n",

				pll->index, status);

		pll_locked = false;
@@ -213,7 +215,7 @@ int dsi_pll_enable_seq_12nm(struct mdss_pll_resources *pll) 
	wmb(); /* make sure register committed before enabling branch clocks */

	udelay(50); /* h/w recommended delay */



	if (!pll_is_pll_locked_12nm(pll)) {

	if (!pll_is_pll_locked_12nm(pll, false)) {

		pr_err("DSI PLL ndx=%d lock failed!\n",

			pll->index);

		rc = -EINVAL;
@@ -261,7 +263,7 @@ static int dsi_pll_relock(struct mdss_pll_resources *pll) 
	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_POWERUP_CTRL, data);

	ndelay(500); /* h/w recommended delay */



	if (!pll_is_pll_locked_12nm(pll)) {

	if (!pll_is_pll_locked_12nm(pll, false)) {

		pr_err("DSI PLL ndx=%d lock failed!\n",

			pll->index);

		rc = -EINVAL;
@@ -710,7 +712,7 @@ enum handoff pll_vco_handoff_12nm(struct clk *c) 
		return ret;

	}



	if (pll_is_pll_locked_12nm(pll)) {

	if (pll_is_pll_locked_12nm(pll, true)) {

		pll->handoff_resources = true;

		pll->pll_on = true;

		c->rate = pll_vco_get_rate_12nm(c);
@@ -756,16 +758,23 @@ int pll_vco_prepare_12nm(struct clk *c) 
					rc, pll->index);

			goto error;

		}

	}



	/*

	 * For cases where  DSI PHY is already enabled like:

	 * 1.) LP-11 during static screen

	 * 2.) ULPS during static screen

	 * 3.) Boot up with cont splash enabled where PHY is programmed in LK

	 * Execute the Re-lock sequence to enable the DSI PLL.

	 */

	data = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_SYS_CTRL);

		if (data & BIT(7)) { /* DSI PHY in LP-11 or ULPS */

	if (data & BIT(7)) {

		rc = dsi_pll_relock(pll);

		if (rc)

			goto error;

		else

			goto end;

	}

	}



	mdss_dsi_pll_12nm_calc_reg(pll, pdb);

drivers/clk/msm/mdss/mdss-dsi-pll-12nm.c

+2 −0
Original line number Diff line number Diff line
@@ -636,11 +636,13 @@ static struct div_clk dsi1pll_byte_clk_src = { 
};



static struct clk_lookup mdss_dsi_pllcc_12nm[] = {

	CLK_LIST(dsi0pll_vco_clk),

	CLK_LIST(dsi0pll_byte_clk_src),

	CLK_LIST(dsi0pll_pixel_clk_src),

};



static struct clk_lookup mdss_dsi_pllcc_12nm_1[] = {

	CLK_LIST(dsi1pll_vco_clk),

	CLK_LIST(dsi1pll_byte_clk_src),

	CLK_LIST(dsi1pll_pixel_clk_src),

};

include/dt-bindings/clock/msm-clocks-8952.h

+2 −0
Original line number Diff line number Diff line
@@ -237,8 +237,10 @@ 


#define clk_dsi0pll_byte_clk_src		0xbbaa30be

#define clk_dsi0pll_pixel_clk_src		0x45b3260f

#define clk_dsi0pll_vco_clk			0x15940d40

#define clk_dsi1pll_byte_clk_src		0x63930a8f

#define clk_dsi1pll_pixel_clk_src		0x0e4c9b56

#define clk_dsi1pll_vco_clk			0x99797b50



#define clk_dsi_pll0_byte_clk_src		0x44539836

#define clk_dsi_pll0_pixel_clk_src		0x5767c287