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Commit 143c7b66 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "power: qpnp-qg: Add support for voltage-only mode of QG"

parents ba2be1b1 1285d002

Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt

+5 −0
Original line number Diff line number Diff line
@@ -308,6 +308,11 @@ First Level Node - QGAUGE device 
	Definition: Boolean property to support external-rsense based

		    configuration.



- qcom,qg-vbms-mode

	Usage:      optional

	Value type: <bool>

	Definition: Boolean property to run QG in Voltage-only mode of QG.



- qcom,shutdown-temp-diff

	Usage:      optional

	Value type: <u32>

drivers/power/supply/qcom/qg-core.h

+2 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ struct qg_dt { 
	bool			esr_disable;

	bool			esr_discharge_enable;

	bool			qg_ext_sense;

	bool			qg_vbms_mode;

};



struct qg_esr_data {
@@ -128,6 +129,7 @@ struct qpnp_qg { 
	int			esr_nominal;

	int			soh;

	int			soc_reporting_ready;

	int			vbms_ibat_ua;

	u32			fifo_done_count;

	u32			wa_flags;

	u32			seq_no;

drivers/power/supply/qcom/qg-reg.h

+1 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ 
#define QG_SDAM_MAX_OFFSET			0xA4



/* Below offset is used by PBS */

#define QG_SDAM_SEQ_OFFSET			0xBB /* 1-byte 0xBB */

#define QG_SDAM_PON_OCV_OFFSET			0xBC /* 2-byte 0xBC-0xBD */



#endif

drivers/power/supply/qcom/qg-util.c

+5 −0
Original line number Diff line number Diff line
@@ -342,6 +342,11 @@ int qg_get_battery_current(struct qpnp_qg *chip, int *ibat_ua) 
		return 0;

	}



	if (chip->dt.qg_vbms_mode) {

		*ibat_ua = chip->vbms_ibat_ua;

		return 0;

	}



	/* hold data */

	rc = qg_masked_write(chip, chip->qg_base + QG_DATA_CTL2_REG,

				BURST_AVG_HOLD_FOR_READ_BIT,

drivers/power/supply/qcom/qpnp-qg.c

+45 −6
Original line number Diff line number Diff line
@@ -1029,6 +1029,9 @@ static void process_udata_work(struct work_struct *work) 
	if (chip->udata.param[QG_FULL_SOC].valid)

		chip->full_soc = chip->udata.param[QG_FULL_SOC].data;



	if (chip->udata.param[QG_VBMS_IBAT].valid)

		chip->vbms_ibat_ua = chip->udata.param[QG_VBMS_IBAT].data;



	if (chip->udata.param[QG_SOC].valid ||

			chip->udata.param[QG_SYS_SOC].valid) {
@@ -1573,7 +1576,8 @@ static int qg_get_ttf_param(void *data, enum ttf_param param, int *val) 


	switch (param) {

	case TTF_VALID:

		*val = (!chip->battery_missing && chip->profile_loaded);

		*val = (!chip->battery_missing && chip->profile_loaded &&

				!chip->dt.qg_vbms_mode);

		break;

	case TTF_MSOC:

		rc = qg_get_battery_capacity(chip, val);
@@ -1791,6 +1795,9 @@ static int qg_psy_get_property(struct power_supply *psy, 
	case POWER_SUPPLY_PROP_CC_SOC:

		rc = qg_get_cc_soc(chip, &pval->intval);

		break;

	case POWER_SUPPLY_PROP_QG_VBMS_MODE:

		pval->intval = !!chip->dt.qg_vbms_mode;

		break;

	default:

		pr_debug("Unsupported property %d\n", psp);

		break;
@@ -1842,6 +1849,7 @@ static enum power_supply_property qg_psy_props[] = { 
	POWER_SUPPLY_PROP_ESR_NOMINAL,

	POWER_SUPPLY_PROP_SOH,

	POWER_SUPPLY_PROP_CC_SOC,

	POWER_SUPPLY_PROP_QG_VBMS_MODE,

};



static const struct power_supply_desc qg_psy_desc = {
@@ -2839,6 +2847,9 @@ static int qg_hw_init(struct qpnp_qg *chip) 
		}

	}



	if (chip->dt.qg_vbms_mode)

		chip->dt.s3_entry_fifo_length = 1;



	if (chip->dt.s3_entry_fifo_length != -EINVAL) {

		if (chip->dt.s3_entry_fifo_length < 1)

			chip->dt.s3_entry_fifo_length = 1;
@@ -2956,6 +2967,11 @@ static int qg_post_init(struct qpnp_qg *chip) 
				PROFILE_IRQ_DISABLE, true, 0);

	}



	if (chip->dt.qg_vbms_mode) {

		chip->dt.esr_disable = true;

		chip->dt.cl_disable = true;

	}



	/* restore ESR data */

	if (!chip->dt.esr_disable)

		qg_retrieve_esr_params(chip);
@@ -3443,18 +3459,24 @@ static int qg_parse_dt(struct qpnp_qg *chip) 
			chip->cl->dt.min_start_soc, chip->cl->dt.max_start_soc,

			chip->cl->dt.min_temp, chip->cl->dt.max_temp);

	}

	qg_dbg(chip, QG_DEBUG_PON, "DT: vbatt_empty_mv=%dmV vbatt_low_mv=%dmV delta_soc=%d ext-sns=%d\n",



	chip->dt.qg_vbms_mode = of_property_read_bool(node,

					"qcom,qg-vbms-mode");



	qg_dbg(chip, QG_DEBUG_PON, "DT: vbatt_empty_mv=%dmV vbatt_low_mv=%dmV delta_soc=%d ext-sns=%d qg_vbms_mode=%d\n",

			chip->dt.vbatt_empty_mv, chip->dt.vbatt_low_mv,

			chip->dt.delta_soc, chip->dt.qg_ext_sense);

			chip->dt.delta_soc, chip->dt.qg_ext_sense,

			chip->dt.qg_vbms_mode);



	return 0;

}



static int process_suspend(struct qpnp_qg *chip)

{

	u8 status = 0;

	u8 status = 0, val;

	int rc;

	u32 fifo_rt_length = 0, sleep_fifo_length = 0;

	bool process_fifo = false;



	/* skip if profile is not loaded */

	if (!chip->profile_loaded)
@@ -3464,6 +3486,12 @@ static int process_suspend(struct qpnp_qg *chip) 


	chip->suspend_data = false;



	val = (chip->seq_no % 128) + 1;

	rc = qg_sdam_multibyte_write(QG_SDAM_SEQ_OFFSET, &val, 1);

	if (rc < 0) {

		pr_err("Failed to write sdam seq, rc=%d\n", rc);

		return rc;

	}

	/* read STATUS2 register to clear its last state */

	qg_read(chip, chip->qg_base + QG_STATUS2_REG, &status, 1);
@@ -3491,7 +3519,13 @@ static int process_suspend(struct qpnp_qg *chip) 
	 * the the #fifo to enter sleep, save the FIFO data

	 * and reset the fifo count.

	 */

	if (fifo_rt_length >= (chip->dt.s2_fifo_length - sleep_fifo_length)) {

	if (chip->dt.qg_vbms_mode && fifo_rt_length >= 1)

		process_fifo = true;

	else if (fifo_rt_length >=

			(chip->dt.s2_fifo_length - sleep_fifo_length))

		process_fifo = true;



	if (process_fifo) {

		rc = qg_master_hold(chip, true);

		if (rc < 0) {

			pr_err("Failed to hold master, rc=%d\n", rc);
@@ -3525,7 +3559,7 @@ static int process_suspend(struct qpnp_qg *chip) 


static int process_resume(struct qpnp_qg *chip)

{

	u8 status2 = 0, rt_status = 0;

	u8 status2 = 0, rt_status = 0, val = 0;

	u32 ocv_uv = 0, ocv_raw = 0;

	int rc;
@@ -3581,6 +3615,11 @@ static int process_resume(struct qpnp_qg *chip) 
		chip->suspend_data = false;

	}



	rc = qg_sdam_multibyte_write(QG_SDAM_SEQ_OFFSET, &val, 1);

	if (rc < 0) {

		pr_err("Failed to write sdam seq, rc=%d\n", rc);

		return rc;

	}

	schedule_delayed_work(&chip->ttf->ttf_work, 0);



	return rc;