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Commit 140e39c1 authored by Huacai Chen's avatar Huacai Chen Committed by Ralf Baechle
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MIPS: Loongson: Modify ChipConfig register definition 



This patch is prepared for Multi-chip interconnection. Since each chip
has a ChipConfig register, LOONGSON_CHIPCFG should be an array.

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7185/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent bda4584c

arch/mips/include/asm/mach-loongson/loongson.h

+5 −2
Original line number Diff line number Diff line
@@ -249,8 +249,11 @@ static inline void do_perfcnt_IRQ(void) 
#define LOONGSON_PXARB_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x68)

#define LOONGSON_PXARB_STATUS		LOONGSON_REG(LOONGSON_REGBASE + 0x6c)



/* Chip Config */

#define LOONGSON_CHIPCFG0		LOONGSON_REG(LOONGSON_REGBASE + 0x80)

#define MAX_PACKAGES 4



/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */

extern u64 loongson_chipcfg[MAX_PACKAGES];

#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))



/* pcimap */

arch/mips/loongson/common/env.c

+11 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ EXPORT_SYMBOL(cpu_clock_freq); 
struct efi_memory_map_loongson *loongson_memmap;

struct loongson_system_configuration loongson_sysconf;



u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};



#define parse_even_earlier(res, option, p)				\

do {									\

	unsigned int tmp __maybe_unused;				\
@@ -77,6 +79,15 @@ void __init prom_init_env(void) 


	cpu_clock_freq = ecpu->cpu_clock_freq;

	loongson_sysconf.cputype = ecpu->cputype;

	if (ecpu->cputype == Loongson_3A) {

		loongson_chipcfg[0] = 0x900000001fe00180;

		loongson_chipcfg[1] = 0x900010001fe00180;

		loongson_chipcfg[2] = 0x900020001fe00180;

		loongson_chipcfg[3] = 0x900030001fe00180;

	} else {

		loongson_chipcfg[0] = 0x900000001fe00180;

	}



	loongson_sysconf.nr_cpus = ecpu->nr_cpus;

	if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)

		loongson_sysconf.nr_cpus = NR_CPUS;

arch/mips/loongson/common/pm.c

+4 −4
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ int __weak wakeup_loongson(void) 
static void wait_for_wakeup_events(void)

{

	while (!wakeup_loongson())

		LOONGSON_CHIPCFG0 &= ~0x7;

		LOONGSON_CHIPCFG(0) &= ~0x7;

}



/*
@@ -102,15 +102,15 @@ static void loongson_suspend_enter(void) 


	stop_perf_counters();



	cached_cpu_freq = LOONGSON_CHIPCFG0;

	cached_cpu_freq = LOONGSON_CHIPCFG(0);



	/* Put CPU into wait mode */

	LOONGSON_CHIPCFG0 &= ~0x7;

	LOONGSON_CHIPCFG(0) &= ~0x7;



	/* wait for the given events to wakeup cpu from wait mode */

	wait_for_wakeup_events();



	LOONGSON_CHIPCFG0 = cached_cpu_freq;

	LOONGSON_CHIPCFG(0) = cached_cpu_freq;

	mmiowb();

}

arch/mips/loongson/lemote-2f/clock.c

+2 −2
Original line number Diff line number Diff line
@@ -114,9 +114,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate) 


	clk->rate = rate;



	regval = LOONGSON_CHIPCFG0;

	regval = LOONGSON_CHIPCFG(0);

	regval = (regval & ~0x7) | (pos->driver_data - 1);

	LOONGSON_CHIPCFG0 = regval;

	LOONGSON_CHIPCFG(0) = regval;



	return ret;

}

arch/mips/loongson/lemote-2f/reset.c

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ static void reset_cpu(void) 
	 * reset cpu to full speed, this is needed when enabling cpu frequency

	 * scalling

	 */

	LOONGSON_CHIPCFG0 |= 0x7;

	LOONGSON_CHIPCFG(0) |= 0x7;

}



/* reset support for fuloong2f */