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Commit 13f659b0 authored by Cyril Chemparathy's avatar Cyril Chemparathy Committed by Will Deacon
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ARM: LPAE: use phys_addr_t in switch_mm() 



This patch modifies the switch_mm() processor functions to use phys_addr_t.
On LPAE systems, we now honor the upper 32-bits of the physical address that
is being passed in, and program these into TTBR as expected.

Signed-off-by: default avatarCyril Chemparathy <cyril@ti.com>
Signed-off-by: default avatarVitaly Andrianov <vitalya@ti.com>
Reviewed-by: default avatarNicolas Pitre <nico@linaro.org>
Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: default avatarSubash Patel <subash.rp@samsung.com>
[will: fixed up conflict in 3-level switch_mm with big-endian changes]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent de22cc6e

arch/arm/include/asm/proc-fns.h

+2 −2
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ extern struct processor { 
	/*

	 * Set the page table

	 */

	void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);

	void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);

	/*

	 * Set a possibly extended PTE.  Non-extended PTEs should

	 * ignore 'ext'.
@@ -82,7 +82,7 @@ extern void cpu_proc_init(void); 
extern void cpu_proc_fin(void);

extern int cpu_do_idle(void);

extern void cpu_dcache_clean_area(void *, int);

extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);

extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);

#ifdef CONFIG_ARM_LPAE

extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);

#else

arch/arm/mm/proc-v7-3level.S

+12 −4
Original line number Diff line number Diff line
@@ -39,6 +39,14 @@ 
#define TTB_FLAGS_SMP	(TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)

#define PMD_FLAGS_SMP	(PMD_SECT_WBWA|PMD_SECT_S)



#ifndef __ARMEB__

#  define rpgdl	r0

#  define rpgdh	r1

#else

#  define rpgdl	r1

#  define rpgdh	r0

#endif



/*

 * cpu_v7_switch_mm(pgd_phys, tsk)

 *
@@ -47,10 +55,10 @@ 
 */

ENTRY(cpu_v7_switch_mm)

#ifdef CONFIG_MMU

	mmid	r1, r1				@ get mm->context.id

	asid	r3, r1

	mov	r3, r3, lsl #(48 - 32)		@ ASID

	mcrr	p15, 0, r0, r3, c2		@ set TTB 0

	mmid	r2, r2

	asid	r2, r2

	orr	rpgdh, rpgdh, r2, lsl #(48 - 32)	@ upper 32-bits of pgd

	mcrr	p15, 0, rpgdl, rpgdh, c2		@ set TTB 0

	isb

#endif

	mov	pc, lr