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Commit 13ec9780 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: add SMART_PANEL_ALIGN_MODE config for split display"

parents 622641e1 15421d85

Documentation/devicetree/bindings/display/msm/sde.txt

+6 −0
Original line number Original line Diff line number Diff line
@@ -125,6 +125,11 @@ Optional properties: 
				configuration value.

				configuration value.

- qcom,sde-ubwc-swizzle:	Property to specify the default UBWC swizzle

- qcom,sde-ubwc-swizzle:	Property to specify the default UBWC swizzle

				configuration value.

				configuration value.

- qcom,sde-smart-panel-align-mode: A u32 property to specify the align mode for

				split display on smart panel. Possible values:

				0x0 - no alignment

				0xc - align at start of frame

				0xd - align at start of line

- qcom,sde-panic-per-pipe:	Boolean property to indicate if panic signal

- qcom,sde-panic-per-pipe:	Boolean property to indicate if panic signal

				control feature is available on each source pipe.

				control feature is available on each source pipe.

- qcom,sde-has-src-split:	Boolean property to indicate if source split

- qcom,sde-has-src-split:	Boolean property to indicate if source split
@@ -535,6 +540,7 @@ Example: 
    qcom,sde-ubwc-version = <0x100>;

    qcom,sde-ubwc-version = <0x100>;

    qcom,sde-ubwc-static = <0x100>;

    qcom,sde-ubwc-static = <0x100>;

    qcom,sde-ubwc-swizzle = <0>;

    qcom,sde-ubwc-swizzle = <0>;

    qcom,sde-smart-panel-align-mode = <0xd>;

    qcom,sde-panic-per-pipe;

    qcom,sde-panic-per-pipe;

    qcom,sde-has-src-split;

    qcom,sde-has-src-split;

    qcom,sde-has-dim-layer;

    qcom,sde-has-dim-layer;

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -148,6 +148,7 @@ enum sde_prop { 
	SMART_DMA_REV,

	SMART_DMA_REV,

	IDLE_PC,

	IDLE_PC,

	DEST_SCALER,

	DEST_SCALER,

	SMART_PANEL_ALIGN_MODE,

	SDE_PROP_MAX,

	SDE_PROP_MAX,

};

};
@@ -403,6 +404,8 @@ static struct sde_prop_type sde_prop[] = { 
	{SMART_DMA_REV, "qcom,sde-smart-dma-rev", false, PROP_TYPE_STRING},

	{SMART_DMA_REV, "qcom,sde-smart-dma-rev", false, PROP_TYPE_STRING},

	{IDLE_PC, "qcom,sde-has-idle-pc", false, PROP_TYPE_BOOL},

	{IDLE_PC, "qcom,sde-has-idle-pc", false, PROP_TYPE_BOOL},

	{DEST_SCALER, "qcom,sde-has-dest-scaler", false, PROP_TYPE_BOOL},

	{DEST_SCALER, "qcom,sde-has-dest-scaler", false, PROP_TYPE_BOOL},

	{SMART_PANEL_ALIGN_MODE, "qcom,sde-smart-panel-align-mode",

			false, PROP_TYPE_U32},

};

};





static struct sde_prop_type sde_perf_prop[] = {

static struct sde_prop_type sde_perf_prop[] = {
@@ -2737,6 +2740,9 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	cfg->mdp[0].has_dest_scaler =

	cfg->mdp[0].has_dest_scaler =

		PROP_VALUE_ACCESS(prop_value, DEST_SCALER, 0);

		PROP_VALUE_ACCESS(prop_value, DEST_SCALER, 0);





	cfg->mdp[0].smart_panel_align_mode =

		PROP_VALUE_ACCESS(prop_value, SMART_PANEL_ALIGN_MODE, 0);



	rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);

	rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);

	if (!rc && !strcmp(type, "qseedv3")) {

	if (!rc && !strcmp(type, "qseedv3")) {

		cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;

		cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -524,6 +524,7 @@ struct sde_clk_ctrl_reg { 
 * @ubwc_static:       ubwc static configuration

 * @ubwc_static:       ubwc static configuration

 * @ubwc_swizzle:      ubwc default swizzle setting

 * @ubwc_swizzle:      ubwc default swizzle setting

 * @has_dest_scaler:   indicates support of destination scaler

 * @has_dest_scaler:   indicates support of destination scaler

 * @smart_panel_align_mode: split display smart panel align modes

 * @clk_ctrls          clock control register definition

 * @clk_ctrls          clock control register definition

 */

 */

struct sde_mdp_cfg {

struct sde_mdp_cfg {
@@ -532,6 +533,7 @@ struct sde_mdp_cfg { 
	u32 ubwc_static;

	u32 ubwc_static;

	u32 ubwc_swizzle;

	u32 ubwc_swizzle;

	bool has_dest_scaler;

	bool has_dest_scaler;

	u32 smart_panel_align_mode;

	struct sde_clk_ctrl_reg clk_ctrls[SDE_CLK_CTRL_MAX];

	struct sde_clk_ctrl_reg clk_ctrls[SDE_CLK_CTRL_MAX];

};

};

drivers/gpu/drm/msm/sde/sde_hw_top.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -86,6 +86,9 @@ static void sde_hw_setup_split_pipe(struct sde_hw_mdp *mdp, 
				lower_pipe = FLD_SMART_PANEL_FREE_RUN;

				lower_pipe = FLD_SMART_PANEL_FREE_RUN;





			upper_pipe = lower_pipe;

			upper_pipe = lower_pipe;



			/* smart panel align mode */

			lower_pipe |= BIT(mdp->caps->smart_panel_align_mode);

		} else {

		} else {

			if (cfg->intf == INTF_2) {

			if (cfg->intf == INTF_2) {

				lower_pipe = FLD_INTF_1_SW_TRG_MUX;

				lower_pipe = FLD_INTF_1_SW_TRG_MUX;