Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 13ad4fd3 authored by Matthew McClintock's avatar Matthew McClintock Committed by Andy Gross
Browse files

qcom: ipq4019: add spi node to ipq4019 SoC and DK01 device tree 



This will allow boards to enable the SPI bus

Signed-off-by: default avatarMatthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 8196dd5e

arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi

+37 −0
Original line number Original line Diff line number Diff line
@@ -48,6 +48,43 @@ 
					bias-disable;

					bias-disable;

				};

				};

			};

			};



			spi_0_pins: spi_0_pinmux {

				pinmux {

					function = "blsp_spi0";

					pins = "gpio55", "gpio56", "gpio57";

				};

				pinmux_cs {

					function = "gpio";

					pins = "gpio54";

				};

				pinconf {

					pins = "gpio55", "gpio56", "gpio57";

					drive-strength = <12>;

					bias-disable;

				};

				pinconf_cs {

					pins = "gpio54";

					drive-strength = <2>;

					bias-disable;

					output-high;

				};

			};

		};



		spi_0: spi@78b5000 {

			pinctrl-0 = <&spi_0_pins>;

			pinctrl-names = "default";

			status = "ok";

			cs-gpios = <&tlmm 54 0>;



			mx25l25635e@0 {

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0>;

				compatible = "mx25l25635e";

				spi-max-frequency = <24000000>;

			};

		};

		};





		serial@78af000 {

		serial@78af000 {

arch/arm/boot/dts/qcom-ipq4019.dtsi

+18 −0
Original line number Original line Diff line number Diff line
@@ -15,12 +15,18 @@ 




#include "skeleton.dtsi"

#include "skeleton.dtsi"

#include <dt-bindings/clock/qcom,gcc-ipq4019.h>

#include <dt-bindings/clock/qcom,gcc-ipq4019.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>





/ {

/ {

	model = "Qualcomm Technologies, Inc. IPQ4019";

	model = "Qualcomm Technologies, Inc. IPQ4019";

	compatible = "qcom,ipq4019";

	compatible = "qcom,ipq4019";

	interrupt-parent = <&intc>;

	interrupt-parent = <&intc>;





	aliases {

		spi0 = &spi_0;

	};



	cpus {

	cpus {

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		#size-cells = <0>;
@@ -108,6 +114,18 @@ 
			interrupts = <0 208 0>;

			interrupts = <0 208 0>;

		};

		};





		spi_0: spi@78b5000 {

			compatible = "qcom,spi-qup-v2.2.1";

			reg = <0x78b5000 0x600>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



                acc0: clock-controller@b088000 {

                acc0: clock-controller@b088000 {

                        compatible = "qcom,kpss-acc-v1";

                        compatible = "qcom,kpss-acc-v1";

                        reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;

                        reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;