Commit 12e669b4 authored Nov 29, 2014 by Jungseung Lee Committed by Russell King Dec 03, 2014

ARM: 8237/1: fix flush_pfn_alias



L1_CACHE_BYTES could be larger than real L1 cache line size.
In that case, flush_pfn_alias() would omit to flush last bytes
as much as L1_CACHE_BYTES - real cache line size.

So fix end address to "to + PAGE_SIZE - 1". The bottom bits of the address
is LINELEN. that is ignored by mcrr.

Signed-off-by: Jungseung Lee <js07.lee@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 80231874

arch/arm/mm/flush.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -33,7 +33,7 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
	asm( "mcrr p15, 0, %1, %0, c14\n"		asm( "mcrr p15, 0, %1, %0, c14\n"
	" mcr p15, 0, %2, c7, c10, 4"		" mcr p15, 0, %2, c7, c10, 4"
	:		:
	: "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)		: "r" (to), "r" (to + PAGE_SIZE - 1), "r" (zero)
	: "cc");		: "cc");
	}		}