Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 12dfc843 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: adjust evergreen display watermark setup 

This patch fixes two issues:
- A disabled crtc does not use any lb, so return 0 for
lb size.  This makes the display priority calculation
more exact.
- Only use 1/2 and whole lb partitions. Using smaller
partitions can cause underflow to one of the displays
if you have multiple large displays on the same lb.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=34534



Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent a70882aa

drivers/gpu/drm/radeon/evergreen.c

+44 −45
Original line number Original line Diff line number Diff line
@@ -353,7 +353,7 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 
					struct drm_display_mode *mode,

					struct drm_display_mode *mode,

					struct drm_display_mode *other_mode)

					struct drm_display_mode *other_mode)

{

{

	u32 tmp = 0;

	u32 tmp;

	/*

	/*

	 * Line Buffer Setup

	 * Line Buffer Setup

	 * There are 3 line buffers, each one shared by 2 display controllers.

	 * There are 3 line buffers, each one shared by 2 display controllers.
@@ -363,37 +363,32 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 
	 * first display controller

	 * first display controller

	 *  0 - first half of lb (3840 * 2)

	 *  0 - first half of lb (3840 * 2)

	 *  1 - first 3/4 of lb (5760 * 2)

	 *  1 - first 3/4 of lb (5760 * 2)

	 *  2 - whole lb (7680 * 2)

	 *  2 - whole lb (7680 * 2), other crtc must be disabled

	 *  3 - first 1/4 of lb (1920 * 2)

	 *  3 - first 1/4 of lb (1920 * 2)

	 * second display controller

	 * second display controller

	 *  4 - second half of lb (3840 * 2)

	 *  4 - second half of lb (3840 * 2)

	 *  5 - second 3/4 of lb (5760 * 2)

	 *  5 - second 3/4 of lb (5760 * 2)

	 *  6 - whole lb (7680 * 2)

	 *  6 - whole lb (7680 * 2), other crtc must be disabled

	 *  7 - last 1/4 of lb (1920 * 2)

	 *  7 - last 1/4 of lb (1920 * 2)

	 */

	 */

	if (mode && other_mode) {

	/* this can get tricky if we have two large displays on a paired group

		if (mode->hdisplay > other_mode->hdisplay) {

	 * of crtcs.  Ideally for multiple large displays we'd assign them to

			if (mode->hdisplay > 2560)

	 * non-linked crtcs for maximum line buffer allocation.

				tmp = 1; /* 3/4 */

	 */

			else

	if (radeon_crtc->base.enabled && mode) {

		if (other_mode)

			tmp = 0; /* 1/2 */

			tmp = 0; /* 1/2 */

		} else if (other_mode->hdisplay > mode->hdisplay) {

			if (other_mode->hdisplay > 2560)

				tmp = 3; /* 1/4 */

		else

		else

				tmp = 0; /* 1/2 */

		} else

			tmp = 0; /* 1/2 */

	} else if (mode)

			tmp = 2; /* whole */

			tmp = 2; /* whole */

	else if (other_mode)

	} else

		tmp = 3; /* 1/4 */

		tmp = 0;





	/* second controller of the pair uses second half of the lb */

	/* second controller of the pair uses second half of the lb */

	if (radeon_crtc->crtc_id % 2)

	if (radeon_crtc->crtc_id % 2)

		tmp += 4;

		tmp += 4;

	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);

	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);





	if (radeon_crtc->base.enabled && mode) {

		switch (tmp) {

		switch (tmp) {

		case 0:

		case 0:

		case 4:

		case 4:
@@ -423,6 +418,10 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 
		}

		}

	}

	}





	/* controller not enabled, so no lb used */

	return 0;

}



static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)

static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)

{

{

	u32 tmp = RREG32(MC_SHARED_CHMAP);

	u32 tmp = RREG32(MC_SHARED_CHMAP);