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Commit 121e09ce authored by Anirudh Ghayal's avatar Anirudh Ghayal
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power: qpnp-qg: Update PON_OCV and GOOD_OCV handling



The QG HW state machine based on the reset / PON conditions
updates the PON SOC at different HW registers. Add the SW
logic to read the PON SOC from LAST_S3 / SDAM / S7_PON
registers.

While at it, enable the GOOD_OCV IRQ only when APPS is not
in sleep.

Change-Id: I1083fe96865c52820a1212882121b4c7f7c8db63
Signed-off-by: default avatarAnirudh Ghayal <aghayal@codeaurora.org>
parent 3716ba43
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+4 −2
Original line number Diff line number Diff line
@@ -115,8 +115,10 @@ struct qpnp_qg {
};

enum ocv_type {
	PON_OCV,
	GOOD_OCV,
	S7_PON_OCV,
	S3_GOOD_OCV,
	S3_LAST_OCV,
	SDAM_PON_OCV,
};

enum debug_mask {
+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@

#define V_RAW_TO_UV(V_RAW)		div_u64(194637ULL * (u64)V_RAW, 1000)
#define I_RAW_TO_UA(I_RAW)		div_s64(152588LL * (s64)I_RAW, 1000)
#define FIFO_V_RESET_VAL		0x8000
#define FIFO_I_RESET_VAL		0x8000

#define DEGC_SCALE			10
#define UV_TO_DECIUV(a)			(a / 100)
+3 −0
Original line number Diff line number Diff line
@@ -77,6 +77,8 @@
#define QG_LAST_ADC_V_DATA0_REG			0xC0
#define QG_LAST_ADC_I_DATA0_REG			0xC2

#define QG_LAST_S3_SLEEP_V_DATA0_REG		0xCC

/* SDAM offsets */
#define QG_SDAM_VALID_OFFSET			0x46
#define QG_SDAM_SOC_OFFSET			0x47
@@ -85,5 +87,6 @@
#define QG_SDAM_OCV_OFFSET			0x4C
#define QG_SDAM_IBAT_OFFSET			0x50
#define QG_SDAM_TIME_OFFSET			0x54
#define QG_SDAM_PON_OCV_OFFSET			0x7C

#endif
+5 −0
Original line number Diff line number Diff line
@@ -63,6 +63,11 @@ static struct qg_sdam_info sdam_info[] = {
		.offset = QG_SDAM_TIME_OFFSET,
		.length = 4,
	},
	[SDAM_PON_OCV_UV] = {
		.name	= "SDAM_PON_OCV",
		.offset = QG_SDAM_PON_OCV_OFFSET,
		.length = 2,
	},
};

int qg_sdam_write(u8 param, u32 data)
+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ enum qg_sdam_param {
	SDAM_OCV_UV,
	SDAM_IBAT_UA,
	SDAM_TIME_SEC,
	SDAM_PON_OCV_UV,
	SDAM_MAX,
};

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