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Commit 11d3623c authored by Osvaldo Banuelos's avatar Osvaldo Banuelos
Browse files

clk: qcom: clk-rpmh: add clk-rpmh driver 



Add the clock RPMh driver to support voting for ARC and
VRM RPMh managed clock resources in some QTI SoCs.

Change-Id: I2bb58a39efb84204aaf65cd5291f55497d1e45ff
Signed-off-by: default avatarOsvaldo Banuelos <osvaldob@codeaurora.org>
parent 88251df7

Documentation/devicetree/bindings/clock/qcom,rpmh.txt

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Original line number Diff line number Diff line 
Qualcomm Technologies, Inc. RPMh Clocks

-------------------------------------------------------



Required properties :

- compatible : must be "qcom,rpmh-clk-sdm845"

- #clock-cells : must contain 1

- mboxes : list of RPMh mailbox phandle and channel identifier tuples.

- mbox-names : list of names to identify the RPMh mailboxes used.

	       Must contain "apps" and optionally "display" if

	       the RPMh mailbox phandle for the Display RSC is

	       specified in the mboxes property.



Example :

	clock_rpmh: qcom,rpmhclk {

		compatible = "qcom,rpmh-clk-sdm845";

		#clock-cells = <1>;

		mboxes = <&apps_rsc 0>, <&disp_rsc 0>;

		mbox-names = "apps", "display";

	};

drivers/clk/qcom/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -177,3 +177,12 @@ config CLOCK_QPNP_DIV 
	  Technologies, Inc. QPNP PMIC. It configures the frequency of

	  clkdiv outputs on the PMIC. These clocks are typically wired

	  through alternate functions on gpio pins.



config MSM_CLK_RPMH

	tristate "RPMh Clock Driver"

	depends on COMMON_CLK_QCOM && QTI_RPMH_API

	help

	  RPMh manages shared resources on some Qualcomm Technologies, Inc.

	  SoCs. It accepts requests from other hardware subsystems via RSC.

	  Say Y to support the clocks managed by RPMh VRM/ARC on platforms

	  such as sdm845.

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -33,3 +33,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o 
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o

obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o

obj-$(CONFIG_CLOCK_QPNP_DIV) += clk-qpnp-div.o

obj-$(CONFIG_MSM_CLK_RPMH) += clk-rpmh.o

drivers/clk/qcom/clk-rpmh.c

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/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <linux/kernel.h>

#include <linux/err.h>

#include <linux/platform_device.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/regmap.h>

#include <soc/qcom/cmd-db.h>

#include <soc/qcom/rpmh.h>

#include <dt-bindings/clock/qcom,rpmh.h>



#include "common.h"

#include "clk-regmap.h"



#define CLK_RPMH_ARC_EN_OFFSET 0

#define CLK_RPMH_VRM_EN_OFFSET 4

#define CLK_RPMH_VRM_OFF_VAL 0

#define CLK_RPMH_VRM_ON_VAL 1

#define CLK_RPMH_APPS_RSC_AO_STATE_MASK (BIT(RPMH_WAKE_ONLY_STATE) | \

					 BIT(RPMH_ACTIVE_ONLY_STATE))

#define CLK_RPMH_APPS_RSC_STATE_MASK (BIT(RPMH_WAKE_ONLY_STATE) | \

				      BIT(RPMH_ACTIVE_ONLY_STATE) | \

				      BIT(RPMH_SLEEP_STATE))



struct clk_rpmh {

	const char *res_name;

	u32 res_addr;

	u32 res_en_offset;

	u32 res_on_val;

	u32 res_off_val;

	u32 state;

	u32 aggr_state;

	u32 last_sent_aggr_state;

	u32 valid_state_mask;

	struct rsc_type *rsc;

	unsigned long rate;

	struct clk_rpmh *peer;

	struct clk_hw hw;

};



struct rsc_type {

	struct rpmh_client *rpmh_client;

	const char *mbox_name;

	const bool use_awake_state;

};



struct rpmh_cc {

	struct clk_onecell_data data;

	struct clk *clks[];

};



struct clk_rpmh_desc {

	struct clk_hw **clks;

	size_t num_clks;

};



static DEFINE_MUTEX(rpmh_clk_lock);



#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \

			  _res_en_offset, _res_on, _res_off, _rsc_id, _rate, \

			  _state_mask, _state_on_mask)			      \

	static struct clk_rpmh _platform##_##_name_active;		      \

	static struct clk_rpmh _platform##_##_name = {			      \

		.res_name = _res_name,					      \

		.res_en_offset = _res_en_offset,			      \

		.res_on_val = _res_on,					      \

		.res_off_val = _res_off,				      \

		.rsc = _rsc_id,						      \

		.rate = _rate,						      \

		.peer = &_platform##_##_name_active,			      \

		.valid_state_mask = _state_mask,			      \

		.hw.init = &(struct clk_init_data){			      \

			.ops = &clk_rpmh_ops,			              \

			.name = #_name,					      \

			.parent_names = (const char *[]){ "xo_board" },       \

			.num_parents = 1,				      \

		},							      \

	};								      \

	static struct clk_rpmh _platform##_##_name_active = {		      \

		.res_name = _res_name,					      \

		.res_en_offset = _res_en_offset,			      \

		.res_on_val = _res_on,					      \

		.res_off_val = _res_off,				      \

		.rsc = _rsc_id,						      \

		.rate = _rate,						      \

		.peer = &_platform##_##_name,				      \

		.valid_state_mask = _state_on_mask,			      \

		.hw.init = &(struct clk_init_data){			      \

			.ops = &clk_rpmh_ops,				      \

			.name = #_name_active,				      \

			.parent_names = (const char *[]){ "xo_board" },	      \

			.num_parents = 1,				      \

		},							      \

	}



#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \

			    _res_on, _res_off, _rsc_id, _rate, _state_mask, \

			    _state_on_mask)				\

	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  CLK_RPMH_ARC_EN_OFFSET, _res_on, _res_off, _rsc_id, \

			  _rate, _state_mask, _state_on_mask)



#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name,	\

			    _rsc_id, _rate, _state_mask, _state_on_mask) \

	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\

			  CLK_RPMH_VRM_EN_OFFSET, CLK_RPMH_VRM_ON_VAL,	\

			  CLK_RPMH_VRM_OFF_VAL, _rsc_id, _rate, _state_mask, \

			  _state_on_mask)



#define DEFINE_RSC_TYPE(name, mbox_id, awake_state)	\

	static struct rsc_type name = {			\

		.rpmh_client = NULL,			\

		.mbox_name = mbox_id,			\

		.use_awake_state = awake_state,		\

	}



static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)

{

	return container_of(_hw, struct clk_rpmh, hw);

}



static inline bool has_state_changed(struct clk_rpmh *c, u32 state)

{

	return ((c->last_sent_aggr_state & BIT(state))

		!= (c->aggr_state & BIT(state)));

}



static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)

{

	struct tcs_cmd cmd = { 0 };

	int ret = 0;



	cmd.addr = c->res_addr + c->res_en_offset;



	if (has_state_changed(c, RPMH_SLEEP_STATE)) {

		cmd.data = (c->aggr_state >> RPMH_SLEEP_STATE) & 1

			? c->res_on_val : c->res_off_val;

		ret = rpmh_write_async(c->rsc->rpmh_client, RPMH_SLEEP_STATE,

				       &cmd, 1);

		if (ret) {

			pr_err("rpmh_write_async(%s, state=%d) failed (%d)\n",

			       c->res_name, RPMH_SLEEP_STATE, ret);

			return ret;

		}

	}



	if (has_state_changed(c, RPMH_WAKE_ONLY_STATE)) {

		cmd.data = (c->aggr_state >> RPMH_WAKE_ONLY_STATE) & 1

			? c->res_on_val : c->res_off_val;

		ret = rpmh_write_async(c->rsc->rpmh_client,

				       RPMH_WAKE_ONLY_STATE, &cmd, 1);

		if (ret) {

			pr_err("rpmh_write_async(%s, state=%d) failed (%d)\n",

			       c->res_name, RPMH_WAKE_ONLY_STATE, ret);

			return ret;

		}

	}



	if (has_state_changed(c, RPMH_ACTIVE_ONLY_STATE)) {

		cmd.data = (c->aggr_state >> RPMH_ACTIVE_ONLY_STATE) & 1

			? c->res_on_val : c->res_off_val;

		ret = rpmh_write(c->rsc->rpmh_client, RPMH_ACTIVE_ONLY_STATE,

				 &cmd, 1);

		if (ret) {

			pr_err("rpmh_write(%s, state=%d) failed (%d)\n",

			       c->res_name, RPMH_ACTIVE_ONLY_STATE, ret);

			return ret;

		}

	}



	if (has_state_changed(c, RPMH_AWAKE_STATE)) {

		cmd.data = (c->aggr_state >> RPMH_AWAKE_STATE) & 1

			? c->res_on_val : c->res_off_val;

		ret = rpmh_write(c->rsc->rpmh_client, RPMH_AWAKE_STATE,

				 &cmd, 1);

		if (ret) {

			pr_err("rpmh_write(%s, state=%d) failed (%d)\n",

			       c->res_name, RPMH_AWAKE_STATE, ret);

			return ret;

		}

	}



	c->last_sent_aggr_state = c->aggr_state;

	c->peer->last_sent_aggr_state =  c->last_sent_aggr_state;



	return 0;

}



static void clk_rpmh_aggregate_state(struct clk_rpmh *c, bool enable)

{

	/* Update state and aggregate state values based on enable value. */

	c->state = enable ? c->valid_state_mask : 0;

	c->aggr_state = c->state | c->peer->state;

	c->peer->aggr_state = c->aggr_state;

}



static int clk_rpmh_prepare(struct clk_hw *hw)

{

	struct clk_rpmh *c = to_clk_rpmh(hw);

	int ret = 0;



	mutex_lock(&rpmh_clk_lock);



	if (c->state)

		goto out;



	clk_rpmh_aggregate_state(c, true);



	ret = clk_rpmh_send_aggregate_command(c);



	if (ret)

		c->state = 0;



out:

	mutex_unlock(&rpmh_clk_lock);

	return ret;

};



static void clk_rpmh_unprepare(struct clk_hw *hw)

{

	struct clk_rpmh *c = to_clk_rpmh(hw);

	int ret = 0;



	mutex_lock(&rpmh_clk_lock);



	if (!c->state)

		goto out;



	clk_rpmh_aggregate_state(c, false);



	ret = clk_rpmh_send_aggregate_command(c);



	if (ret) {

		c->state = c->valid_state_mask;

		WARN(1, "%s failed to disable\n", c->res_name);

	}



out:

	mutex_unlock(&rpmh_clk_lock);

	return;

};



static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,

					  unsigned long parent_rate)

{

	struct clk_rpmh *r = to_clk_rpmh(hw);



	/*

	 * RPMh clocks have a fixed rate. Return static rate set

	 * at init time.

	 */

	return r->rate;

}



static const struct clk_ops clk_rpmh_ops = {

	.prepare	= clk_rpmh_prepare,

	.unprepare	= clk_rpmh_unprepare,

	.recalc_rate	= clk_rpmh_recalc_rate,

};



/* Use awake state instead of active-only on RSCs that do not have an AMC. */

DEFINE_RSC_TYPE(apps_rsc, "apps", false);

DEFINE_RSC_TYPE(disp_rsc, "display", true);



/* Resource name must match resource id present in cmd-db. */

DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 0x0,

		    &apps_rsc, 19200000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);

DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", &apps_rsc,

		    19200000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);

DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", &apps_rsc,

		    19200000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);

DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", &apps_rsc,

		    19200000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);

DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", &apps_rsc,

		    38400000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);

DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", &apps_rsc,

		    38400000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);

DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", &apps_rsc,

		    38400000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);



static struct clk_hw *sdm845_rpmh_clocks[] = {

	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,

	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,

	[RPMH_LN_BB_CLK1]	= &sdm845_ln_bb_clk1.hw,

	[RPMH_LN_BB_CLK1_A]	= &sdm845_ln_bb_clk1_ao.hw,

	[RPMH_LN_BB_CLK2]	= &sdm845_ln_bb_clk2.hw,

	[RPMH_LN_BB_CLK2_A]	= &sdm845_ln_bb_clk2_ao.hw,

	[RPMH_LN_BB_CLK3]	= &sdm845_ln_bb_clk3.hw,

	[RPMH_LN_BB_CLK3_A]	= &sdm845_ln_bb_clk3_ao.hw,

	[RPMH_RF_CLK1]		= &sdm845_rf_clk1.hw,

	[RPMH_RF_CLK1_A]	= &sdm845_rf_clk1_ao.hw,

	[RPMH_RF_CLK2]		= &sdm845_rf_clk2.hw,

	[RPMH_RF_CLK2_A]	= &sdm845_rf_clk2_ao.hw,

	[RPMH_RF_CLK3]		= &sdm845_rf_clk3.hw,

	[RPMH_RF_CLK3_A]	= &sdm845_rf_clk3_ao.hw,

};



static const struct clk_rpmh_desc clk_rpmh_sdm845 = {

	.clks = sdm845_rpmh_clocks,

	.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),

};



static const struct of_device_id clk_rpmh_match_table[] = {

	{ .compatible = "qcom,rpmh-clk-sdm845", .data = &clk_rpmh_sdm845},

	{ }

};

MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);



static int clk_rpmh_probe(struct platform_device *pdev)

{

	struct clk **clks;

	struct clk *clk;

	struct rpmh_cc *rcc;

	struct clk_onecell_data *data;

	int ret;

	size_t num_clks, i;

	struct clk_hw **hw_clks;

	struct clk_rpmh *rpmh_clk;

	const struct clk_rpmh_desc *desc;

	struct property *prop;

	const char *mbox_name;



	desc = of_device_get_match_data(&pdev->dev);

	if (!desc) {

		ret = -EINVAL;

		goto err;

	}



	ret = cmd_db_ready();

	if (ret) {

		if (ret != -EPROBE_DEFER) {

			dev_err(&pdev->dev, "Command DB not available (%d)\n",

				ret);

			goto err;

		}

		return ret;

	}



	of_property_for_each_string(pdev->dev.of_node, "mbox-names", prop,

				    mbox_name) {

		if (!strcmp(apps_rsc.mbox_name, mbox_name)) {

			apps_rsc.rpmh_client = rpmh_get_byname(pdev, mbox_name);

			if (IS_ERR(apps_rsc.rpmh_client)) {

				ret = PTR_ERR(apps_rsc.rpmh_client);

				if (ret != -EPROBE_DEFER) {

					dev_err(&pdev->dev,

						"failed to request RPMh client for %s (%d)\n",

						mbox_name, ret);

					goto err;

				}

				return ret;

			}

		}



		if (!strcmp(disp_rsc.mbox_name, mbox_name)) {

			disp_rsc.rpmh_client = rpmh_get_byname(pdev, mbox_name);

			if (IS_ERR(disp_rsc.rpmh_client)) {

				ret = PTR_ERR(disp_rsc.rpmh_client);

				if (ret != -EPROBE_DEFER) {

					dev_err(&pdev->dev,

						"failed to request RPMh client for %s (%d)\n",

						mbox_name, ret);

					goto err2;

				}

				return ret;

			}

		}

	}



	if (!apps_rsc.rpmh_client) {

		dev_err(&pdev->dev, "%s mbox is missing\n", apps_rsc.mbox_name);

		ret = -EINVAL;

		goto err2;

	}



	hw_clks = desc->clks;

	num_clks = desc->num_clks;



	rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*clks) * num_clks,

			   GFP_KERNEL);

	if (!rcc) {

		ret = -ENOMEM;

		goto err2;

	}



	clks = rcc->clks;

	data = &rcc->data;

	data->clks = clks;

	data->clk_num = num_clks;



	for (i = 0; i < num_clks; i++) {

		rpmh_clk = to_clk_rpmh(hw_clks[i]);

		rpmh_clk->res_addr = cmd_db_get_addr(rpmh_clk->res_name);

		if (!rpmh_clk->res_addr) {

			dev_err(&pdev->dev, "missing RPMh resource address for %s\n",

				rpmh_clk->res_name);

			ret = -ENODEV;

			goto err2;

		}



		clk = devm_clk_register(&pdev->dev, hw_clks[i]);

		if (IS_ERR(clk)) {

			ret = PTR_ERR(clk);

			goto err2;

		}



		clks[i] = clk;

	}



	ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,

				  data);

	if (ret)

		goto err2;



	dev_info(&pdev->dev, "Registered RPMh clocks\n");

	return ret;



err2:

	rpmh_release(apps_rsc.rpmh_client);

	if (disp_rsc.rpmh_client)

		rpmh_release(disp_rsc.rpmh_client);

err:

	dev_err(&pdev->dev, "Error registering RPMh Clock driver (%d)\n", ret);

	return ret;

}



static struct platform_driver clk_rpmh_driver = {

	.probe		= clk_rpmh_probe,

	.driver		= {

		.name	= "clk-rpmh",

		.of_match_table = clk_rpmh_match_table,

	},

};



static int __init clk_rpmh_init(void)

{

	return platform_driver_register(&clk_rpmh_driver);

}

core_initcall(clk_rpmh_init);



static void __exit clk_rpmh_exit(void)

{

	platform_driver_unregister(&clk_rpmh_driver);

}

module_exit(clk_rpmh_exit);



MODULE_DESCRIPTION("QTI RPMh Clock Driver");

MODULE_LICENSE("GPL v2");

MODULE_ALIAS("platform:clk-rpmh");

include/dt-bindings/clock/qcom,rpmh.h

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/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H

#define _DT_BINDINGS_CLK_MSM_RPMH_H



/* RPMh controlled clocks */

#define RPMH_CXO_CLK						0

#define RPMH_CXO_CLK_A						1

#define RPMH_LN_BB_CLK1						2

#define RPMH_LN_BB_CLK1_A					3

#define RPMH_LN_BB_CLK2						4

#define RPMH_LN_BB_CLK2_A					5

#define RPMH_LN_BB_CLK3						6

#define RPMH_LN_BB_CLK3_A					7

#define RPMH_RF_CLK1						8

#define RPMH_RF_CLK1_A						9

#define RPMH_RF_CLK2						10

#define RPMH_RF_CLK2_A						11

#define RPMH_RF_CLK3						12

#define RPMH_RF_CLK3_A						13

#define RPMH_QDSS_CLK						14

#define RPMH_QDSS_A_CLK						15



#endif