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Commit 113d0f9d authored by Marek Olšák's avatar Marek Olšák Committed by Alex Deucher
Browse files

drm/radeon: allow TA_CS_BC_BASE_ADDR on SI 



Required for border colors in compute shaders.

Reviewed-by: default avatarEdward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarMarek Olšák <marek.olsak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce199ad6

drivers/gpu/drm/radeon/radeon_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -96,9 +96,10 @@ 
 *   2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI

 *   2.46.0 - Add PFP_SYNC_ME support on evergreen

 *   2.47.0 - Add UVD_NO_OP register support

 *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI

 */

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MINOR	47

#define KMS_DRIVER_MINOR	48

#define KMS_DRIVER_PATCHLEVEL	0

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);

int radeon_driver_unload_kms(struct drm_device *dev);

drivers/gpu/drm/radeon/si.c

+1 −0
Original line number Diff line number Diff line
@@ -4431,6 +4431,7 @@ static bool si_vm_reg_valid(u32 reg) 
	case SPI_CONFIG_CNTL:

	case SPI_CONFIG_CNTL_1:

	case TA_CNTL_AUX:

	case TA_CS_BC_BASE_ADDR:

		return true;

	default:

		DRM_ERROR("Invalid register 0x%x in CS\n", reg);

drivers/gpu/drm/radeon/sid.h

+1 −0
Original line number Diff line number Diff line
@@ -1145,6 +1145,7 @@ 
#define	SPI_LB_CU_MASK					0x9354



#define	TA_CNTL_AUX					0x9508

#define	TA_CS_BC_BASE_ADDR				0x950C



#define CC_RB_BACKEND_DISABLE				0x98F4

#define		BACKEND_DISABLE(x)     			((x) << 16)