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Commit 1072856a authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv50: add memory type detection 



DDR1/DDR[23] confirmed on NVA8 (see note about DDR3 in source) by changing
the value and watching the binary driver's behaviour.

GDDR3/4 values confirmed on a NV96 via the same method above.  That GDDR4
is present is interesting, as far as I can see no boards using it were ever
released.

GDDR5 value is based on VBIOS images of known GDDR5 boards.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent ff92a6cd

drivers/gpu/drm/nouveau/nv50_vram.c

+16 −0
Original line number Diff line number Diff line
@@ -189,8 +189,24 @@ nv50_vram_init(struct drm_device *dev) 
	struct nouveau_vram_engine *vram = &dev_priv->engine.vram;

	const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */

	const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */

	u32 pfb714 = nv_rd32(dev, 0x100714);

	u32 rblock, length;



	switch (pfb714 & 0x00000007) {

	case 0: dev_priv->vram_type = NV_MEM_TYPE_DDR1; break;

	case 1:

		if (0 /* some currently unknown condition */)

			dev_priv->vram_type = NV_MEM_TYPE_DDR2;

		else

			dev_priv->vram_type = NV_MEM_TYPE_DDR3;

		break;

	case 2: dev_priv->vram_type = NV_MEM_TYPE_GDDR3; break;

	case 3: dev_priv->vram_type = NV_MEM_TYPE_GDDR4; break;

	case 4: dev_priv->vram_type = NV_MEM_TYPE_GDDR5; break;

	default:

		break;

	}



	dev_priv->vram_size  = nv_rd32(dev, 0x10020c);

	dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;

	dev_priv->vram_size &= 0xffffffff00ULL;