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Commit 10126ac1 authored by Keith Busch's avatar Keith Busch Committed by Bjorn Helgaas
Browse files

PCI: Add Downstream Port Containment portdrv service type 



Add the Downstream Port Containment (PCIE_PORT_SERVICE_DPC) portdrv service
type, available if the device has the DPC extended capability.

[bhelgaas: split to separate patch, changelog]
Signed-off-by: default avatarKeith Busch <keith.busch@intel.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 6d81417d

drivers/pci/pcie/portdrv.h

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 


#include <linux/compiler.h>



#define PCIE_PORT_DEVICE_MAXSERVICES   4

#define PCIE_PORT_DEVICE_MAXSERVICES   5

/*

 * According to the PCI Express Base Specification 2.0, the indices of

 * the MSI-X table entries used by port services must not exceed 31

drivers/pci/pcie/portdrv_acpi.c

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ int pcie_port_acpi_setup(struct pci_dev *port, int *srv_mask) 


	flags = root->osc_control_set;



	*srv_mask = PCIE_PORT_SERVICE_VC;

	*srv_mask = PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;

	if (flags & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)

		*srv_mask |= PCIE_PORT_SERVICE_HP;

	if (flags & OSC_PCI_EXPRESS_PME_CONTROL)

drivers/pci/pcie/portdrv_core.c

+3 −1
Original line number Diff line number Diff line
@@ -262,7 +262,7 @@ static int get_port_device_capability(struct pci_dev *dev) 
		return 0;



	cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP

			| PCIE_PORT_SERVICE_VC;

			| PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;

	if (pci_aer_available())

		cap_mask |= PCIE_PORT_SERVICE_AER;
@@ -311,6 +311,8 @@ static int get_port_device_capability(struct pci_dev *dev) 
		 */

		pcie_pme_interrupt_enable(dev, false);

	}

	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC))

		services |= PCIE_PORT_SERVICE_DPC;



	return services;

}

include/linux/pcieport_if.h

+2 −0
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 
#define PCIE_PORT_SERVICE_HP		(1 << PCIE_PORT_SERVICE_HP_SHIFT)

#define PCIE_PORT_SERVICE_VC_SHIFT	3	/* Virtual Channel */

#define PCIE_PORT_SERVICE_VC		(1 << PCIE_PORT_SERVICE_VC_SHIFT)

#define PCIE_PORT_SERVICE_DPC_SHIFT	4	/* Downstream Port Containment */

#define PCIE_PORT_SERVICE_DPC		(1 << PCIE_PORT_SERVICE_DPC_SHIFT)



struct pcie_device {

	int		irq;	    /* Service IRQ/MSI/MSI-X Vector */

include/uapi/linux/pci_regs.h

+2 −1
Original line number Diff line number Diff line
@@ -670,7 +670,8 @@ 
#define PCI_EXT_CAP_ID_SECPCI	0x19	/* Secondary PCIe Capability */

#define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */

#define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */

#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PASID

#define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */

#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DPC



#define PCI_EXT_CAP_DSN_SIZEOF	12

#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40