x86/fpu: Remove use_eager_fpu() (0fd0aa78) · Commits · e / devices / android_kernel_fairphone_FP3

arch/x86/crypto/crc32c-intel_glue.c

+4 −13

Original line number	Diff line number	Diff line
		@@ -48,21 +48,13 @@
		#ifdef CONFIG_X86_64
		/*
		* use carryless multiply version of crc32c when buffer
		* size is >= 512 (when eager fpu is enabled) or
		* >= 1024 (when eager fpu is disabled) to account
		* size is >= 512 to account
		* for fpu state save/restore overhead.
		*/
		#define CRC32C_PCL_BREAKEVEN_EAGERFPU 512
		#define CRC32C_PCL_BREAKEVEN_NOEAGERFPU 1024
		#define CRC32C_PCL_BREAKEVEN 512

		asmlinkage unsigned int crc_pcl(const u8 *buffer, int len,
		unsigned int crc_init);
		static int crc32c_pcl_breakeven = CRC32C_PCL_BREAKEVEN_EAGERFPU;
		#define set_pcl_breakeven_point() \
		do { \
		if (!use_eager_fpu()) \
		crc32c_pcl_breakeven = CRC32C_PCL_BREAKEVEN_NOEAGERFPU; \
		} while (0)
		#endif /* CONFIG_X86_64 */

		static u32 crc32c_intel_le_hw_byte(u32 crc, unsigned char const *data, size_t length)
		@@ -185,7 +177,7 @@ static int crc32c_pcl_intel_update(struct shash_desc desc, const u8 data,
		* use faster PCL version if datasize is large enough to
		* overcome kernel fpu state save/restore overhead
		*/
		if (len >= crc32c_pcl_breakeven && irq_fpu_usable()) {
		if (len >= CRC32C_PCL_BREAKEVEN && irq_fpu_usable()) {
		kernel_fpu_begin();
		crcp = crc_pcl(data, len, crcp);
		kernel_fpu_end();
		@@ -197,7 +189,7 @@ static int crc32c_pcl_intel_update(struct shash_desc desc, const u8 data,
		static int __crc32c_pcl_intel_finup(u32 crcp, const u8 data, unsigned int len,
		u8 *out)
		{
		if (len >= crc32c_pcl_breakeven && irq_fpu_usable()) {
		if (len >= CRC32C_PCL_BREAKEVEN && irq_fpu_usable()) {
		kernel_fpu_begin();
		(__le32 )out = ~cpu_to_le32(crc_pcl(data, len, *crcp));
		kernel_fpu_end();
		@@ -257,7 +249,6 @@ static int __init crc32c_intel_mod_init(void)
		alg.update = crc32c_pcl_intel_update;
		alg.finup = crc32c_pcl_intel_finup;
		alg.digest = crc32c_pcl_intel_digest;
		set_pcl_breakeven_point();
		}
		#endif
		return crypto_register_shash(&alg);

arch/x86/include/asm/fpu/internal.h

+1 −33

Original line number	Diff line number	Diff line
		@@ -60,11 +60,6 @@ extern u64 fpu__get_supported_xfeatures_mask(void);
		/*
		* FPU related CPU feature flag helper routines:
		*/
		static __always_inline __pure bool use_eager_fpu(void)
		{
		return true;
		}

		static __always_inline __pure bool use_xsaveopt(void)
		{
		return static_cpu_has(X86_FEATURE_XSAVEOPT);
		@@ -501,24 +496,6 @@ static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu)
		}


		/*
		* Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation'
		* idiom, which is then paired with the sw-flag (fpregs_active) later on:
		*/

		static inline void __fpregs_activate_hw(void)
		{
		if (!use_eager_fpu())
		clts();
		}

		static inline void __fpregs_deactivate_hw(void)
		{
		if (!use_eager_fpu())
		stts();
		}

		/* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */
		static inline void __fpregs_deactivate(struct fpu *fpu)
		{
		WARN_ON_FPU(!fpu->fpregs_active);
		@@ -528,7 +505,6 @@ static inline void __fpregs_deactivate(struct fpu *fpu)
		trace_x86_fpu_regs_deactivated(fpu);
		}

		/* Must be paired with a 'clts' (fpregs_activate_hw()) before! */
		static inline void __fpregs_activate(struct fpu *fpu)
		{
		WARN_ON_FPU(fpu->fpregs_active);
		@@ -554,22 +530,17 @@ static inline int fpregs_active(void)
		}

		/*
		* Encapsulate the CR0.TS handling together with the
		* software flag.
		*
		* These generally need preemption protection to work,
		* do try to avoid using these on their own.
		*/
		static inline void fpregs_activate(struct fpu *fpu)
		{
		__fpregs_activate_hw();
		__fpregs_activate(fpu);
		}

		static inline void fpregs_deactivate(struct fpu *fpu)
		{
		__fpregs_deactivate(fpu);
		__fpregs_deactivate_hw();
		}

		/*
		@@ -596,8 +567,7 @@ switch_fpu_prepare(struct fpu old_fpu, struct fpu new_fpu, int cpu)
		* or if the past 5 consecutive context-switches used math.
		*/
		fpu.preload = static_cpu_has(X86_FEATURE_FPU) &&
		new_fpu->fpstate_active &&
		(use_eager_fpu() \|\| new_fpu->counter > 5);
		new_fpu->fpstate_active;

		if (old_fpu->fpregs_active) {
		if (!copy_fpregs_to_fpstate(old_fpu))
		@@ -615,8 +585,6 @@ switch_fpu_prepare(struct fpu old_fpu, struct fpu new_fpu, int cpu)
		__fpregs_activate(new_fpu);
		trace_x86_fpu_regs_activated(new_fpu);
		prefetch(&new_fpu->state);
		} else {
		__fpregs_deactivate_hw();
		}
		} else {
		old_fpu->counter = 0;

arch/x86/kernel/fpu/core.c

+4 −32

Original line number	Diff line number	Diff line
		@@ -59,27 +59,9 @@ static bool kernel_fpu_disabled(void)
		return this_cpu_read(in_kernel_fpu);
		}

		/*
		* Were we in an interrupt that interrupted kernel mode?
		*
		* On others, we can do a kernel_fpu_begin/end() pair ONLY if that
		* pair does nothing at all: the thread must not have fpu (so
		* that we don't try to save the FPU state), and TS must
		* be set (so that the clts/stts pair does nothing that is
		* visible in the interrupted kernel thread).
		*
		* Except for the eagerfpu case when we return true; in the likely case
		* the thread has FPU but we are not going to set/clear TS.
		*/
		static bool interrupted_kernel_fpu_idle(void)
		{
		if (kernel_fpu_disabled())
		return false;

		if (use_eager_fpu())
		return true;

		return !current->thread.fpu.fpregs_active && (read_cr0() & X86_CR0_TS);
		return !kernel_fpu_disabled();
		}

		/*
		@@ -127,7 +109,6 @@ void __kernel_fpu_begin(void)
		copy_fpregs_to_fpstate(fpu);
		} else {
		this_cpu_write(fpu_fpregs_owner_ctx, NULL);
		__fpregs_activate_hw();
		}
		}
		EXPORT_SYMBOL(__kernel_fpu_begin);
		@@ -138,8 +119,6 @@ void __kernel_fpu_end(void)

		if (fpu->fpregs_active)
		copy_kernel_to_fpregs(&fpu->state);
		else
		__fpregs_deactivate_hw();

		kernel_fpu_enable();
		}
		@@ -201,10 +180,7 @@ void fpu__save(struct fpu *fpu)
		trace_x86_fpu_before_save(fpu);
		if (fpu->fpregs_active) {
		if (!copy_fpregs_to_fpstate(fpu)) {
		if (use_eager_fpu())
		copy_kernel_to_fpregs(&fpu->state);
		else
		fpregs_deactivate(fpu);
		}
		}
		trace_x86_fpu_after_save(fpu);
		@@ -262,7 +238,6 @@ int fpu__copy(struct fpu dst_fpu, struct fpu src_fpu)
		* Don't let 'init optimized' areas of the XSAVE area
		* leak into the child task:
		*/
		if (use_eager_fpu())
		memset(&dst_fpu->state.xsave, 0, fpu_kernel_xstate_size);

		/*
		@@ -285,10 +260,7 @@ int fpu__copy(struct fpu dst_fpu, struct fpu src_fpu)
		memcpy(&src_fpu->state, &dst_fpu->state,
		fpu_kernel_xstate_size);

		if (use_eager_fpu())
		copy_kernel_to_fpregs(&src_fpu->state);
		else
		fpregs_deactivate(src_fpu);
		}
		preempt_enable();

arch/x86/kernel/fpu/signal.c

+3 −5

Original line number	Diff line number	Diff line
		@@ -344,11 +344,9 @@ static int __fpu__restore_sig(void __user buf, void __user buf_fx, int size)
		}

		fpu->fpstate_active = 1;
		if (use_eager_fpu()) {
		preempt_disable();
		fpu__restore(fpu);
		preempt_enable();
		}

		return err;
		} else {

arch/x86/kernel/fpu/xstate.c

+0 −9

Original line number	Diff line number	Diff line
		@@ -890,15 +890,6 @@ int arch_set_user_pkey_access(struct task_struct *tsk, int pkey,
		*/
		if (!boot_cpu_has(X86_FEATURE_OSPKE))
		return -EINVAL;
		/*
		* For most XSAVE components, this would be an arduous task:
		* brining fpstate up to date with fpregs, updating fpstate,
		* then re-populating fpregs. But, for components that are
		* never lazily managed, we can just access the fpregs
		* directly. PKRU is never managed lazily, so we can just
		* manipulate it directly. Make sure it stays that way.
		*/
		WARN_ON_ONCE(!use_eager_fpu());

		/* Set the bits we need in PKRU: */
		if (init_val & PKEY_DISABLE_ACCESS)