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Commit 0fc03d4c authored by Russell King's avatar Russell King
Browse files

ARM: SMP enable of cache maintanence broadcast 



Masahiro Yamada reports that we can fail to set the FW bit in the
auxiliary control register, which enables broadcasting the cache
maintanence operations.  This occurs because we only check that the
SMP/nAMP bit is set, rather than checking whether all the bits we
want to be set are set.

Rearrange the code to ensure that all desired bits are set, and only
update the register if we discover some required bits are not set.

Tested-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent f55532a0

arch/arm/mm/proc-v7.S

+5 −5
Original line number Diff line number Diff line
@@ -281,12 +281,12 @@ __v7_ca17mp_setup: 
	bl      v7_invalidate_l1

	ldmia	r12, {r1-r6, lr}

#ifdef CONFIG_SMP

	orr	r10, r10, #(1 << 6)		@ Enable SMP/nAMP mode

	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)

	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP

	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?

	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode

	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits

	mcreq	p15, 0, r0, c1, c0, 1

	ALT_UP(mov	r0, r10)		@ fake it for UP

	orr	r10, r10, r0			@ Set required bits

	teq	r10, r0				@ Were they already set?

	mcrne	p15, 0, r10, c1, c0, 1		@ No, update register

#endif

	b	__v7_setup_cont