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Commit 0fb4c9fc authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: gcc-sdm845: Add GCC clock programming support for SDM845 v2.1 



The gcc_aggre_noc_pcie_tbu_clk clock that needed to be kept
enabled always on previous versions of the target can now
be gated on SDM845 v2.1. Add support to allow toggling it.

Change-Id: I6ba66e09ec827f319e54a82e49ec21e9f1da6524
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 8072741f

Documentation/devicetree/bindings/clock/qcom,gcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ Required properties : 
			"qcom,gcc-mdm9615"

			"qcom,gcc-sdm845"

			"qcom,gcc-sdm845-v2"

			"qcom,gcc-sdm845-v2.1"

			"qcom,gcc-sdm670"

			"qcom,debugcc-sdm845"

drivers/clk/qcom/gcc-sdm845.c

+5 −3
Original line number Diff line number Diff line
@@ -4068,6 +4068,7 @@ static const struct qcom_cc_desc gcc_sdm845_desc = { 
static const struct of_device_id gcc_sdm845_match_table[] = {

	{ .compatible = "qcom,gcc-sdm845" },

	{ .compatible = "qcom,gcc-sdm845-v2" },

	{ .compatible = "qcom,gcc-sdm845-v2.1" },

	{ .compatible = "qcom,gcc-sdm670" },

	{ }

};
@@ -4267,7 +4268,8 @@ static int gcc_sdm845_fixup(struct platform_device *pdev) 
	if (!compat || (compatlen <= 0))

		return -EINVAL;



	if (!strcmp(compat, "qcom,gcc-sdm845-v2"))

	if (!strcmp(compat, "qcom,gcc-sdm845-v2") ||

			!strcmp(compat, "qcom,gcc-sdm845-v2.1"))

		gcc_sdm845_fixup_sdm845v2();

	else if (!strcmp(compat, "qcom,gcc-sdm670"))

		gcc_sdm845_fixup_sdm670();
@@ -4322,8 +4324,8 @@ static int gcc_sdm845_probe(struct platform_device *pdev) 
	regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);

	regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);



	/* Keep this clock on all the time on SDM845 v1 */

	if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-sdm845"))

	/* Keep this clock on all the times except on SDM845 v2.1 */

	if (!of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-sdm845-v2.1"))

		clk_prepare_enable(gcc_aggre_noc_pcie_tbu_clk.clkr.hw.clk);



	/* DFS clock registration */