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Commit 0fab541a authored by Or Gerlitz's avatar Or Gerlitz Committed by David S. Miller
Browse files

net/mlx4_core: Fix misleading debug print on CQE stride support 



We do support cache line sizes of 32 and 64 bytes without activating the
CQE stride feature. Fix a misleading print saying that these cache line
sizes aren't supported.

Signed-off-by: default avatarOr Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: default avatarAmir Vadai <amirv@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6af0a52f

drivers/net/ethernet/mellanox/mlx4/main.c

+2 −1
Original line number Diff line number Diff line
@@ -251,7 +251,8 @@ static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 
		if (mlx4_is_master(dev))

			dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;

	} else {

		mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");

		if (cache_line_size() != 32  && cache_line_size() != 64)

			mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");

		dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;

		dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;

	}