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Commit 0f97e35b authored by Deepak Kumar's avatar Deepak Kumar
Browse files

msm: kgsl: Correct GPU busy counter overflow detection 



Correct overflow detection check to return true only if
previous value of register ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI
is less than current value.

Also, update the counter variable to current counter value
incase where abnormal counter value is observed to make sure
next GPU busy sample is correct.

Change-Id: If2d504791123eedf1dca3bdc85ff0166c1e8ae13
Signed-off-by: default avatarDeepak Kumar <dkumar@codeaurora.org>
parent a385b633

drivers/gpu/msm/adreno.h

+11 −5
Original line number Diff line number Diff line
@@ -1805,7 +1805,7 @@ static inline bool is_power_counter_overflow(struct adreno_device *adreno_dev, 
		return ret;

	}

	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI, &val);

	if (val != *perfctr_pwr_hi) {

	if (val > *perfctr_pwr_hi) {

		*perfctr_pwr_hi = val;

		ret = true;

	}
@@ -1820,14 +1820,17 @@ static inline unsigned int counter_delta(struct kgsl_device *device, 
	unsigned int ret = 0;

	bool overflow = true;

	static unsigned int perfctr_pwr_hi;

	unsigned int prev_perfctr_pwr_hi = 0;



	/* Read the value */

	kgsl_regread(device, reg, &val);



	if (adreno_is_a5xx(adreno_dev) && reg == adreno_getreg

		(adreno_dev, ADRENO_REG_RBBM_PERFCTR_RBBM_0_LO))

		(adreno_dev, ADRENO_REG_RBBM_PERFCTR_RBBM_0_LO)) {

		prev_perfctr_pwr_hi = perfctr_pwr_hi;

		overflow = is_power_counter_overflow(adreno_dev, reg,

				*counter, &perfctr_pwr_hi);

	}



	/* Return 0 for the first read */

	if (*counter != 0) {
@@ -1840,9 +1843,12 @@ static inline unsigned int counter_delta(struct kgsl_device *device, 
			 * Since KGSL got abnormal value from the counter,

			 * We will drop the value from being accumulated.

			 */

			pr_warn_once("KGSL: Abnormal value :0x%x (0x%x) from perf counter : 0x%x\n",

					val, *counter, reg);

			return 0;

			KGSL_DRV_ERR_RATELIMIT(device,

				"Abnormal value:0x%llx (0x%llx) from perf counter : 0x%x\n",

				val | ((uint64_t)perfctr_pwr_hi << 32),

				*counter |

					((uint64_t)prev_perfctr_pwr_hi << 32),

				reg);

		}

	}