Merge "msm: sde: add support for ubwc 2.0 to sde rotator" into msm-4.9 (0f72f180) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/media/video/msm-sde-rotator.txt

+7 −1

Original line number	Diff line number	Diff line
		@@ -89,6 +89,10 @@ Optional properties
		entries by name.
		- cache-slices: The tuple has phandle to llcc device as the first argument and the
		second argument is the usecase id of the client.
		- qcom,sde-ubwc-malsize: A u32 property to specify the default UBWC
		minimum allowable length configuration value.
		- qcom,sde-ubwc-swizzle: A u32 property to specify the default UBWC
		swizzle configuration value.

		Subnode properties:
		- compatible: Compatible name used in smmu v2.
		@@ -126,6 +130,8 @@ Example:
		clock-names = "iface_clk", "rot_core_clk";

		qcom,mdss-highest-bank-bit = <0x2>;
		qcom,sde-ubwc-malsize = <0>;
		qcom,sde-ubwc-swizzle = <1>;

		/* Bus Scale Settings */
		qcom,msm-bus,name = "mdss_rotator";
		@@ -144,7 +150,7 @@ Example:

		qcom,mdss-sbuf-headroom = <20>;
		cache-slice-names = "rotator";
		cache-slices = <&llcc 3>;
		cache-slices = <&llcc 4>;

		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
		compatible = "qcom,smmu_sde_rot_unsec";

drivers/media/platform/msm/sde/rotator/sde_rotator_base.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -98,6 +98,7 @@ enum sde_rot_type {
		* @SDE_CAPS_R3_1P5_DOWNSCALE: 1.5x downscale rotator support
		* @SDE_CAPS_MIN_BUS_VOTE: minimum bus vote prior to power enable
		* @SDE_CAPS_SBUF_1: stream buffer support for inline rotation
		* @SDE_CAPS_UBWC_2: universal bandwidth compression version 2
		*/
		enum sde_caps_settings {
		SDE_CAPS_R1_WB,
		@@ -106,6 +107,7 @@ enum sde_caps_settings {
		SDE_CAPS_SEC_ATTACH_DETACH_SMMU,
		SDE_CAPS_MIN_BUS_VOTE,
		SDE_CAPS_SBUF_1,
		SDE_CAPS_UBWC_2,
		SDE_CAPS_MAX,
		};

drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c

+35 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,8 @@

		/* default stream buffer headroom in lines */
		#define DEFAULT_SBUF_HEADROOM 20
		#define DEFAULT_UBWC_MALSIZE 1
		#define DEFAULT_UBWC_SWIZZLE 1

		/* Macro for constructing the REGDMA command */
		#define SDE_REGDMA_WRITE(p, off, data) \
		@@ -877,6 +879,12 @@ static void sde_hw_rotator_setup_fetchengine(struct sde_hw_rotator_context *ctx,
		SDE_ROT_SSPP_FETCH_CONFIG_RESET_VALUE \|
		((rot->highest_bank & 0x3) << 18));

		if (test_bit(SDE_CAPS_UBWC_2, mdata->sde_caps_map))
		SDE_REGDMA_WRITE(wrptr, ROT_SSPP_UBWC_STATIC_CTRL, BIT(31) \|
		((ctx->rot->ubwc_malsize & 0x3) << 8) \|
		((ctx->rot->highest_bank & 0x3) << 4) \|
		((ctx->rot->ubwc_swizzle & 0x1) << 0));

		/* setup source buffer plane security status */
		if (flags & (SDE_ROT_FLAG_SECURE_OVERLAY_SESSION \|
		SDE_ROT_FLAG_SECURE_CAMERA_SESSION)) {
		@@ -1009,6 +1017,12 @@ static void sde_hw_rotator_setup_wbengine(struct sde_hw_rotator_context *ctx,
		SDE_REGDMA_WRITE(wrptr, ROT_WB_DST_WRITE_CONFIG,
		(ctx->rot->highest_bank & 0x3) << 8);

		if (test_bit(SDE_CAPS_UBWC_2, mdata->sde_caps_map))
		SDE_REGDMA_WRITE(wrptr, ROT_WB_UBWC_STATIC_CTRL,
		((ctx->rot->ubwc_malsize & 0x3) << 8) \|
		((ctx->rot->highest_bank & 0x3) << 4) \|
		((ctx->rot->ubwc_swizzle & 0x1) << 0));

		if (test_bit(SDE_CAPS_SBUF_1, mdata->sde_caps_map))
		SDE_REGDMA_WRITE(wrptr, ROT_WB_SYS_CACHE_MODE,
		ctx->sys_cache_mode);
		@@ -2212,6 +2226,7 @@ static int sde_rotator_hw_rev_init(struct sde_hw_rotator *rot)
		SDEROT_DBG("Supporting sys cache inline rotation\n");
		set_bit(SDE_CAPS_MIN_BUS_VOTE, mdata->sde_caps_map);
		set_bit(SDE_CAPS_SBUF_1, mdata->sde_caps_map);
		set_bit(SDE_CAPS_UBWC_2, mdata->sde_caps_map);
		rot->inpixfmts = sde_hw_rotator_v4_inpixfmts;
		rot->num_inpixfmt = ARRAY_SIZE(sde_hw_rotator_v4_inpixfmts);
		rot->outpixfmts = sde_hw_rotator_v4_outpixfmts;
		@@ -2738,6 +2753,26 @@ static int sde_hw_rotator_parse_dt(struct sde_hw_rotator *hw_data,
		hw_data->highest_bank = data;
		}

		ret = of_property_read_u32(dev->dev.of_node,
		"qcom,sde-ubwc-malsize", &data);
		if (ret) {
		ret = 0;
		hw_data->ubwc_malsize = DEFAULT_UBWC_MALSIZE;
		} else {
		SDEROT_DBG("set ubwc malsize to %d\n", data);
		hw_data->ubwc_malsize = data;
		}

		ret = of_property_read_u32(dev->dev.of_node,
		"qcom,sde-ubwc_swizzle", &data);
		if (ret) {
		ret = 0;
		hw_data->ubwc_swizzle = DEFAULT_UBWC_SWIZZLE;
		} else {
		SDEROT_DBG("set ubwc swizzle to %d\n", data);
		hw_data->ubwc_swizzle = data;
		}

		ret = of_property_read_u32(dev->dev.of_node,
		"qcom,mdss-sbuf-headroom", &data);
		if (ret) {

drivers/media/platform/msm/sde/rotator/sde_rotator_r3_hwio.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -70,6 +70,7 @@
		#define ROT_SSPP_SRC_UNPACK_PATTERN (SDE_ROT_SSPP_OFFSET+0x34)
		#define ROT_SSPP_SRC_OP_MODE (SDE_ROT_SSPP_OFFSET+0x38)
		#define ROT_SSPP_SRC_CONSTANT_COLOR (SDE_ROT_SSPP_OFFSET+0x3C)
		#define ROT_SSPP_UBWC_STATIC_CTRL (SDE_ROT_SSPP_OFFSET+0x44)
		#define ROT_SSPP_FETCH_CONFIG (SDE_ROT_SSPP_OFFSET+0x48)
		#define ROT_SSPP_VC1_RANGE (SDE_ROT_SSPP_OFFSET+0x4C)
		#define ROT_SSPP_REQPRIORITY_FIFO_WATERMARK_0 (SDE_ROT_SSPP_OFFSET+0x50)

drivers/media/platform/msm/sde/rotator/sde_rotator_r3_internal.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -248,6 +248,9 @@ struct sde_hw_rotator_resource_info {
		* struct sde_hw_rotator : Rotator description
		* @hw: mdp register mapped offset
		* @ops: pointer to operations possible for the rotator HW
		* @highest_bank: highest bank size of memory
		* @ubwc_malsize: ubwc minimum allowable length
		* @ubwc_swizzle: ubwc swizzle enable
		* @sbuf_headroom: stream buffer headroom in lines
		* @solid_fill: true if solid fill is requested
		* @constant_color: solid fill constant color
		@@ -296,6 +299,8 @@ struct sde_hw_rotator {
		void *swts_buffer;

		u32 highest_bank;
		u32 ubwc_malsize;
		u32 ubwc_swizzle;
		u32 sbuf_headroom;
		u32 solid_fill;
		u32 constant_color;