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Commit 0ef2481c authored by Asutosh Das's avatar Asutosh Das Committed by xiaonian
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mmc: host: add SDHCI platform driver for msm chipsets



This platform driver adds the support of Secure Digital Host
Controller Interface compliant controller in MSM chipsets.

Change-Id: Ide3a658ad51a3c3d4a05c47c0e8f013f647c9516
Signed-off-by: default avatarAsutosh Das <asutoshd@codeaurora.org>
Signed-off-by: default avatarVenkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fix trivial merge conflicts and Changed
Qualcomm to Qualcomm Technologies, Inc.]
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
[xiaonian@codeaurora.org: fix trivial merge conflict]
Signed-off-by: default avatarXiaonian Wang <xiaonian@codeaurora.org>
parent 5209be96
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+67 −41
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* Qualcomm SDHCI controller (sdhci-msm)
Qualcomm Technologies, Inc. Standard Secure Digital Host Controller (SDHC)

This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci-msm driver.
Secure Digital Host Controller provides standard host interface to SD/MMC/SDIO cards.

Required properties:
- compatible: Should contain "qcom,sdhci-msm-v4".
- reg: Base address and length of the register in the following order:
	- Host controller register map (required)
	- SD Core register map (required)
- interrupts: Should contain an interrupt-specifiers for the interrupts:
	- Host controller interrupt (required)
- pinctrl-names: Should contain only one value - "default".
- pinctrl-0: Should specify pin control groups used for this controller.
- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
- clock-names: Should contain the following:
	"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
	"core"	- SDC MMC clock (MCLK) (required)
	"bus"	- SDCC bus voter clock (optional)
  - compatible : should be "qcom,sdhci-msm"
  - reg : should contain SDHC, SD Core register map.
  - reg-names : indicates various resources passed to driver (via reg proptery) by name.
		Required "reg-names" are "hc_mem" and "core_mem"
  - interrupts : should contain SDHC interrupts.
  - interrupt-names : indicates interrupts passed to driver (via interrupts property) by name.
		      Required "interrupt-names" are "hc_irq" and "pwr_irq".
  - <supply-name>-supply: phandle to the regulator device tree node
			  Required "supply-name" are "vdd" and "vdd-io".

Example:
Required alias:
- The slot number is specified via an alias with the following format
	'sdhc{n}' where n is the slot number.

	sdhc_1: sdhci@f9824900 {
		compatible = "qcom,sdhci-msm-v4";
		reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
		interrupts = <0 123 0>;
		bus-width = <8>;
		non-removable;
Optional Properties:
	- interrupt-names - "status_irq". This status_irq will be used for card
			     detection.
	- qcom,bus-width - defines the bus I/O width that controller supports.
			   Units - number of bits. The valid bus-width values are
			   1, 4 and 8.
	- qcom,nonremovable - specifies whether the card in slot is
			      hot pluggable or hard wired.
	- qcom,bus-speed-mode - specifies supported bus speed modes by host.
				The supported bus speed modes are :
				"HS200_1p8v" - indicates that host can support HS200 at 1.8v.
				"HS200_1p2v" - indicates that host can support HS200 at 1.2v.
				"DDR_1p8v" - indicates that host can support DDR mode at 1.8v.
				"DDR_1p2v" - indicates that host can support DDR mode at 1.2v.

In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage).
	- qcom,<supply>-always-on - specifies whether supply should be kept "on" always.
	- qcom,<supply>-lpm_sup - specifies whether supply can be kept in low power mode (lpm).
	- qcom,<supply>-voltage_level - specifies voltage levels for supply. Should be
					specified in pairs (min, max), units uV.
	- qcom,<supply>-current_level - specifies load levels for supply in lpm or
					high power mode (hpm). Should be specified in
					pairs (lpm, hpm), units uA.

		vmmc-supply = <&pm8941_l20>;
		vqmmc-supply = <&pm8941_s3>;
	- gpios - specifies gpios assigned for sdhc slot.
	- qcom,gpio-names -  a list of strings that map in order to the list of gpios

		pinctrl-names = "default";
		pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
Example:

		clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
		clock-names = "core", "iface";
	aliases {
		sdhc1 = &sdhc_1;
	};

	sdhc_2: sdhci@f98a4900 {
		compatible = "qcom,sdhci-msm-v4";
		reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
		interrupts = <0 125 0>;
		bus-width = <4>;
		cd-gpios = <&msmgpio 62 0x1>;
	sdhc_1: qcom,sdhc@f9824900 {
		compatible = "qcom,sdhci-msm";
                reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
                reg-names = "hc_mem", "core_mem";
                interrupts = <0 123 0>, <0 138 0>;
                interrupt-names = "hc_irq", "pwr_irq";

		vdd-supply = <&pm8941_l21>;
		vdd-io-supply = <&pm8941_l13>;
		qcom,vdd-voltage-level = <2950000 2950000>;
		qcom,vdd-current-level = <9000 800000>;

		vmmc-supply = <&pm8941_l21>;
		vqmmc-supply = <&pm8941_l13>;
		qcom,vdd-io-always-on;
		qcom,vdd-io-lpm-sup;
		qcom,vdd-io-voltage-level = <1800000 2950000>;
		qcom,vdd-io-current-level = <6 22000>;

		pinctrl-names = "default";
		pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
                qcom,bus-width = <4>;
		qcom,nonremovable;
		qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";

		clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
		clock-names = "core", "iface";
		gpios = <&msmgpio 40 0>, /* CLK */
			<&msmgpio 39 0>, /* CMD */
			<&msmgpio 38 0>, /* DATA0 */
			<&msmgpio 37 0>, /* DATA1 */
			<&msmgpio 36 0>, /* DATA2 */
			<&msmgpio 35 0>; /* DATA3 */
		qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
	};
+13 −0
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@@ -395,6 +395,19 @@ config MMC_ATMELMCI

	  If unsure, say N.

config MMC_SDHCI_MSM
	tristate "Qualcomm Technologies, Inc. SDHCI Controller Support"
	depends on ARCH_QCOM || ARCH_MSM || (ARM && COMPILE_TEST)
	depends on MMC_SDHCI_PLTFM
	help
	  This selects the Secure Digital Host Controller Interface (SDHCI)
	  support present in Qualcomm Technologies, Inc. SOCs. The controller
	  supports SD/MMC/SDIO devices.

	  If you have a controller with this interface, say Y or M here.

	  If unsure, say N.

config MMC_MSM
	tristate "Qualcomm SDCC Controller Support"
	depends on MMC && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50)
+1 −0
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@@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
obj-$(CONFIG_MMC_SDHCI_MSM)		+= sdhci-msm.o
obj-$(CONFIG_MMC_SDHCI_IPROC)		+= sdhci-iproc.o
obj-$(CONFIG_MMC_SDHCI_ST)		+= sdhci-st.o
obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32)	+= sdhci-pic32.o
+983 −0

File changed.

Preview size limit exceeded, changes collapsed.

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@@ -23,6 +23,7 @@ struct sdhci_pltfm_data {

struct sdhci_pltfm_host {
	struct clk *clk;
	void *priv; /* to handle quirks across io-accessor calls */

	/* migrate from sdhci_of_host */
	unsigned int clock;
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