Loading arch/arm/boot/dts/qcom/sdxpoorwills-rumi.dts +1 −0 Original line number Diff line number Diff line Loading @@ -26,4 +26,5 @@ &blsp1_uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_console_active>; status = "ok"; }; arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -153,5 +153,8 @@ reg = <0x831000 0x200>; interrupts = <0 26 0>; status = "disabled"; clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; }; }; Loading
arch/arm/boot/dts/qcom/sdxpoorwills-rumi.dts +1 −0 Original line number Diff line number Diff line Loading @@ -26,4 +26,5 @@ &blsp1_uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_console_active>; status = "ok"; };
arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -153,5 +153,8 @@ reg = <0x831000 0x200>; interrupts = <0 26 0>; status = "disabled"; clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; }; };