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Commit 0e7b833e authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add additional CPU clock frequencies on SDM845 



Add the remaining PORed CPU clock frequencies along with their
corresponding configurations on SDM845.

Change-Id: Iff69bcd46d3fc1cbceb619de126be5d11447c703
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent deda3be7

arch/arm64/boot/dts/qcom/sdm845.dtsi

+20 −3
Original line number Diff line number Diff line
@@ -1031,7 +1031,9 @@ 
			<   576000000 0x5014031e 0x00002020 0x1 4 >,

			<   652800000 0x401c0422 0x00002020 0x1 5 >,

			<   729600000 0x401c0526 0x00002020 0x1 6 >,

			<   806400000 0x401c062a 0x00002222 0x1 7 >;

			<   806400000 0x401c062a 0x00002222 0x1 7 >,

			<   883200000 0x4024072e 0x00002525 0x2 8 >,

			<   960000000 0x40240832 0x00002828 0x2 9 >;



		qcom,pwrcl-speedbin0-v0 =

			<   300000000 0x000c000f 0x00002020 0x1 1 >,
@@ -1045,7 +1047,12 @@ 
			<   979200000 0x40240833 0x00002929 0x1 9 >,

			<  1056000000 0x402c0937 0x00002c2c 0x1 10 >,

			<  1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,

			<  1209600000 0x402c0b3f 0x00003333 0x1 12 >;

			<  1209600000 0x402c0b3f 0x00003333 0x1 12 >,

			<  1286400000 0x40340c43 0x00003636 0x2 13 >,

			<  1363200000 0x40340d47 0x00003939 0x2 14 >,

			<  1440000000 0x40340e4b 0x00003c3c 0x2 15 >,

			<  1516800000 0x403c0f4f 0x00003f3f 0x2 16 >,

			<  1593600000 0x403c1053 0x00004242 0x2 17 >;



		qcom,perfcl-speedbin0-v0 =

			<   300000000 0x000c000f 0x00002020 0x1 1 >,
@@ -1059,7 +1066,17 @@ 
			<   960000000 0x40240832 0x00002828 0x1 9 >,

			<  1036800000 0x40240936 0x00002b2b 0x1 10 >,

			<  1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,

			<  1190400000 0x402c0b3e 0x00003232 0x1 12 >;

			<  1190400000 0x402c0b3e 0x00003232 0x1 12 >,

			<  1267200000 0x40340c42 0x00003535 0x2 13 >,

			<  1344000000 0x40340d46 0x00003838 0x2 14 >,

			<  1420800000 0x40340e4a 0x00003b3b 0x2 15 >,

			<  1497600000 0x403c0f4e 0x00003e3e 0x2 16 >,

			<  1574400000 0x403c1052 0x00004242 0x2 17 >,

			<  1651200000 0x403c1156 0x00004545 0x2 18 >,

			<  1728000000 0x4044125a 0x00004848 0x3 19 >,

			<  1804800000 0x4044135e 0x00004b4b 0x3 20 >,

			<  1881600000 0x404c1462 0x00004e4e 0x3 21 >,

			<  1958400000 0x404c1566 0x00005252 0x3 22 >;



		qcom,l3-min-cpr-vc-bin0 = <7>;

		qcom,pwrcl-min-cpr-vc-bin0 = <6>;