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Commit 0e660cb0 authored by Kyle Yan's avatar Kyle Yan
Browse files

soc: qcom: pil: Add PDC sync register to modem PIL flow on SDM845 



PDC is a new block to SDM845 that is needed in the bootup and shutdown
sequences of modem.

Change-Id: I93f5a4be4015942be0a73853e619d50b64705d51
Signed-off-by: default avatarKyle Yan <kyan@codeaurora.org>
parent 7fc1bbb1

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ Required properties: 
		      If "halt_base" is in same 4K pages this register then

		      this will be defined else "halt_q6", "halt_modem",

		      "halt_nc" is required.

		      "pdc_sync" is the power domain register introduced in

		      sdm845 for power domain of subsystems.

- interrupts:         The modem watchdog interrupt

- vdd_cx-supply:      Reference to the regulator that supplies the vdd_cx domain.

- vdd_cx-voltage:     Voltage corner/level(max) for cx rail.

drivers/soc/qcom/pil-msa.c

+25 −0
Original line number Diff line number Diff line
@@ -75,6 +75,10 @@ 
#define MSS_RESTART_ID			0xA



#define MSS_MAGIC			0XAABADEAD



#define MSS_PDC_OFFSET			8

#define MSS_PDC_MASK			BIT(MSS_PDC_OFFSET)



enum scm_cmd {

	PAS_MEM_SETUP_CMD = 2,

};
@@ -204,6 +208,23 @@ static void pil_mss_disable_clks(struct q6v5_data *drv) 
		clk_disable_unprepare(drv->ahb_clk);

}



static void pil_mss_pdc_sync(struct q6v5_data *drv, bool pdc_sync)

{

	u32 val = 0;



	if (drv->pdc_sync) {

		val = readl_relaxed(drv->pdc_sync);

		if (pdc_sync)

			val |= MSS_PDC_MASK;

		else

			val &= ~MSS_PDC_MASK;

		writel_relaxed(val, drv->pdc_sync);

		/* Ensure PDC is written before next write */

		wmb();

		udelay(2);

	}

}



static int pil_mss_restart_reg(struct q6v5_data *drv, u32 mss_restart)

{

	int ret = 0;
@@ -304,6 +325,7 @@ int pil_mss_shutdown(struct pil_desc *pil) 
									ret);

	}



	pil_mss_pdc_sync(drv, 1);

	ret = pil_mss_restart_reg(drv, 1);



	if (drv->is_booted) {
@@ -468,6 +490,8 @@ static int pil_mss_reset(struct pil_desc *pil) 
	if (ret)

		goto err_restart;



	pil_mss_pdc_sync(drv, 0);



	ret = pil_mss_enable_clks(drv);

	if (ret)

		goto err_clks;
@@ -523,6 +547,7 @@ static int pil_mss_reset(struct pil_desc *pil) 
	if (drv->ahb_clk_vote)

		clk_disable_unprepare(drv->ahb_clk);

err_clks:

	pil_mss_pdc_sync(drv, 1);

	pil_mss_restart_reg(drv, 1);

err_restart:

	pil_mss_power_down(drv);

drivers/soc/qcom/pil-q6v5-mss.c

+7 −0
Original line number Diff line number Diff line
@@ -284,6 +284,13 @@ static int pil_mss_loadable_init(struct modem_data *drv, 
	if (!q6->restart_reg)

		return -ENOMEM;



	q6->pdc_sync = NULL;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pdc_sync");

	if (res) {

		q6->pdc_sync = devm_ioremap(&pdev->dev,

						res->start, resource_size(res));

	}



	q6->vreg = NULL;



	prop = of_find_property(pdev->dev.of_node, "vdd_mss-supply", NULL);

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ struct q6v5_data { 
	void __iomem *axi_halt_mss;

	void __iomem *axi_halt_nc;

	void __iomem *restart_reg;

	void __iomem *pdc_sync;

	struct regulator *vreg;

	struct regulator *vreg_cx;

	struct regulator *vreg_mx;