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Commit 0de1fb12 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.9.290 into android-4.9-q 



Changes in 4.9.290
	scsi: core: Put LLD module refcnt after SCSI device is released
	mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS
	arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed
	ARM: 9120/1: Revert "amba: make use of -1 IRQs warn"
	net: hso: register netdev later to avoid a race condition
	usb: hso: fix error handling code of hso_create_net_device
	Revert "x86/kvm: fix vcpu-id indexed array sizes"
	IB/qib: Use struct_size() helper
	IB/qib: Protect from buffer overflow in struct qib_user_sdma_pkt fields
	usb: gadget: Mark USB_FSL_QE broken on 64-bit
	usb: musb: Balance list entry in musb_gadget_queue
	usb-storage: Add compatibility quirk flags for iODD 2531/2541
	printk/console: Allow to disable console output by using console="" or console=null
	isofs: Fix out of bound access for corrupted isofs image
	comedi: dt9812: fix DMA buffers on stack
	comedi: ni_usb6501: fix NULL-deref in command paths
	comedi: vmk80xx: fix transfer-buffer overflows
	comedi: vmk80xx: fix bulk-buffer overflow
	comedi: vmk80xx: fix bulk and interrupt message timeouts
	staging: r8712u: fix control-message timeout
	staging: rtl8192u: fix control-message timeouts
	rsi: fix control-message timeout
	Linux 4.9.290

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: I91380c82e93a66d0c1738c710264741b907553c1
parents 09db023b ab95ef83

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 9

SUBLEVEL = 289

SUBLEVEL = 290

EXTRAVERSION =

NAME = Roaring Lionus

arch/arc/include/asm/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -137,8 +137,10 @@ 


#ifdef CONFIG_ARC_HAS_PAE40

#define PTE_BITS_NON_RWX_IN_PD1	(0xff00000000 | PAGE_MASK | _PAGE_CACHEABLE)

#define MAX_POSSIBLE_PHYSMEM_BITS 40

#else

#define PTE_BITS_NON_RWX_IN_PD1	(PAGE_MASK | _PAGE_CACHEABLE)

#define MAX_POSSIBLE_PHYSMEM_BITS 32

#endif



/**************************************************************************

arch/arm/include/asm/pgtable-2level.h

+2 −0
Original line number Diff line number Diff line
@@ -78,6 +78,8 @@ 
#define PTE_HWTABLE_OFF		(PTE_HWTABLE_PTRS * sizeof(pte_t))

#define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u32))



#define MAX_POSSIBLE_PHYSMEM_BITS	32



/*

 * PMD_SHIFT determines the size of the area a second-level page table can map

 * PGDIR_SHIFT determines what a third-level page table entry can map

arch/arm/include/asm/pgtable-3level.h

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ 
#define PTE_HWTABLE_OFF		(0)

#define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u64))



#define MAX_POSSIBLE_PHYSMEM_BITS 40



/*

 * PGDIR_SHIFT determines the size a top-level page table entry can map.

 */

arch/mips/include/asm/pgtable-32.h

+3 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ static inline void pmd_clear(pmd_t *pmdp) 


#if defined(CONFIG_XPA)



#define MAX_POSSIBLE_PHYSMEM_BITS 40

#define pte_pfn(x)		(((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))

static inline pte_t

pfn_pte(unsigned long pfn, pgprot_t prot)
@@ -125,6 +126,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot) 


#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)



#define MAX_POSSIBLE_PHYSMEM_BITS 36

#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))



static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
@@ -139,6 +141,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 


#else



#define MAX_POSSIBLE_PHYSMEM_BITS 32

#ifdef CONFIG_CPU_VR41XX

#define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))

#define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))