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Commit 0d0dd036 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "phy: qcom-ufs-qmp-v3: remove legacy v3 phy support" into msm-4.9

parents e2caec41 e5bb92bd

drivers/phy/phy-qcom-ufs-qmp-v3.c

+2 −51
Original line number Diff line number Diff line
@@ -23,26 +23,12 @@ int ufs_qcom_phy_qmp_v3_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, 
	int err;

	int tbl_size_A, tbl_size_B;

	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;

	u8 major = ufs_qcom_phy->host_ctrl_rev_major;

	u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;

	u16 step = ufs_qcom_phy->host_ctrl_rev_step;



	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);

	tbl_B = phy_cal_table_rate_B;



	if ((major == 0x3) && (minor == 0x000) && (step == 0x0000)) {

		tbl_A = phy_cal_table_rate_A_3_0_0;

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_0_0);

	} else if ((major == 0x3) && (minor == 0x001) && (step == 0x0000)) {

		tbl_A = phy_cal_table_rate_A_3_1_0;

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_1_0);

	} else {

		dev_err(ufs_qcom_phy->dev,

			"%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n",

			__func__, major, minor, step);

		err = -ENODEV;

		goto out;

	}

	tbl_A = phy_cal_table_rate_A;

	tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);



	err = ufs_qcom_phy_calibrate(ufs_qcom_phy,

				     tbl_A, tbl_size_A,
@@ -54,7 +40,6 @@ int ufs_qcom_phy_qmp_v3_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, 
			"%s: ufs_qcom_phy_calibrate() failed %d\n",

			__func__, err);



out:

	return err;

}
@@ -161,39 +146,6 @@ static int ufs_qcom_phy_qmp_v3_is_pcs_ready(struct ufs_qcom_phy *phy_common) 
	return err;

}



static

int ufs_qcom_phy_qmp_v3_configure_lpm(struct ufs_qcom_phy *ufs_qcom_phy,

					bool enable)

{

	int err = 0;

	int tbl_size;

	struct ufs_qcom_phy_calibration *tbl = NULL;



	/* The default low power mode configuration is SVS2 */

	if (enable) {

		tbl_size = ARRAY_SIZE(phy_cal_table_svs2_enable);

		tbl = phy_cal_table_svs2_enable;

	} else {

		tbl_size = ARRAY_SIZE(phy_cal_table_svs2_disable);

		tbl = phy_cal_table_svs2_disable;

	}



	if (!tbl) {

		dev_err(ufs_qcom_phy->dev, "%s: tbl for SVS2 %s is NULL",

			__func__, enable ? "enable" : "disable");

		err = -EINVAL;

		goto out;

	}



	ufs_qcom_phy_write_tbl(ufs_qcom_phy, tbl, tbl_size);



	/* flush buffered writes */

	mb();



out:

	return err;

}



static void ufs_qcom_phy_qmp_v3_dbg_register_dump(struct ufs_qcom_phy *phy)

{

	ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
@@ -225,7 +177,6 @@ struct ufs_qcom_phy_specific_ops phy_v3_ops = { 
	.set_tx_lane_enable	= ufs_qcom_phy_qmp_v3_set_tx_lane_enable,

	.ctrl_rx_linecfg	= ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg,

	.power_control		= ufs_qcom_phy_qmp_v3_power_control,

	.configure_lpm		= ufs_qcom_phy_qmp_v3_configure_lpm,

	.dbg_register_dump	= ufs_qcom_phy_qmp_v3_dbg_register_dump,

};

drivers/phy/phy-qcom-ufs-qmp-v3.h

+1 −93
Original line number Diff line number Diff line
@@ -208,67 +208,7 @@ struct ufs_qcom_phy_qmp_v3 { 
	struct ufs_qcom_phy common_cfg;

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_0_0[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD5),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0A),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x08),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x34),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0xCB),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x08),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x34),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xB2),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_INTERFACE_MODE, 0x40),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x5B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN, 0x04),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0xF1),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6C),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0x9A), /* 8 us */

};



static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_1_0[] = {

static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD5),
@@ -352,36 +292,4 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { 
	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44),

};



static struct ufs_qcom_phy_calibration phy_cal_table_svs2_enable[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE0, 0x14),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x14),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x0a),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x7e),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x06),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x7e),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x99),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x07),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x0b),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x66),

};



static struct ufs_qcom_phy_calibration phy_cal_table_svs2_disable[] = {

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE0, 0x0a),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),

	UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x16),

	UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0xcc),

};



#endif

drivers/scsi/ufs/ufs-qcom.c

+0 −48
Original line number Diff line number Diff line
@@ -2252,38 +2252,6 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 
	return err;

}



static inline int ufs_qcom_configure_lpm(struct ufs_hba *hba, bool enable)

{

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);

	struct phy *phy = host->generic_phy;

	int err = 0;



	/* The default low power mode configuration is SVS2 */

	if (!ufs_qcom_cap_svs2(host))

		goto out;



	if (!((host->hw_ver.major == 0x3) &&

	    (host->hw_ver.minor == 0x0) &&

	    (host->hw_ver.step == 0x0)))

		goto out;



	/*

	 * The link should be put in hibern8 state before

	 * configuring the PHY to enter/exit SVS2 mode.

	 */

	err = ufshcd_uic_hibern8_enter(hba);

	if (err)

		goto out;



	err = ufs_qcom_phy_configure_lpm(phy, enable);

	if (err)

		goto out;



	err = ufshcd_uic_hibern8_exit(hba);

out:

	return err;

}



static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)

{

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -2293,10 +2261,6 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 
	if (!ufs_qcom_cap_qunipro(host))

		goto out;



	err = ufs_qcom_configure_lpm(hba, false);

	if (err)

		goto out;



	if (attr)

		__ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,

				      attr->hs_rate, false, true);
@@ -2307,16 +2271,6 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 
	return err;

}



static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)

{

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);



	if (!ufs_qcom_cap_qunipro(host))

		return 0;



	return ufs_qcom_configure_lpm(hba, true);

}



static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)

{

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -2356,8 +2310,6 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 
	case PRE_CHANGE:

		if (scale_up)

			err = ufs_qcom_clk_scale_up_pre_change(hba);

		else

			err = ufs_qcom_clk_scale_down_pre_change(hba);

		break;

	case POST_CHANGE:

		if (!scale_up)