Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0cac1eea authored by Channagoud Kadabi's avatar Channagoud Kadabi
Browse files

arch: arm64: Add midr values for kryo3xx big cores 



Add midr value for kryo3xx big cores to apply errata workarounds for
branch prediction hardening.

Change-Id: I235e88fc0595931f58f4a7a399a1015dad17c1b5
Signed-off-by: default avatarChannagoud Kadabi <ckadabi@codeaurora.org>
parent bd5269e7

arch/arm64/include/asm/cputype.h

+2 −1
Original line number Diff line number Diff line
@@ -63,7 +63,6 @@ 
({									\

	u32 _model = (midr) & MIDR_CPU_MODEL_MASK;			\

	u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);	\

									\

	_model == (model) && rv >= (rv_min) && rv <= (rv_max);		\

 })
@@ -80,6 +79,7 @@ 
#define ARM_CPU_PART_CORTEX_A53		0xD03

#define ARM_CPU_PART_CORTEX_A73		0xD09

#define ARM_CPU_PART_CORTEX_A75		0xD0A

#define ARM_CPU_PART_KRYO3G		0x802



#define APM_CPU_PART_POTENZA		0x000
@@ -93,6 +93,7 @@ 
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)

#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)

#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)

#define MIDR_KRYO3G	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO3G)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

arch/arm64/kernel/cpu_errata.c

+5 −0
Original line number Diff line number Diff line
@@ -252,6 +252,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),

		.enable = enable_psci_bp_hardening,

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		MIDR_ALL_VERSIONS(MIDR_KRYO3G),

		.enable = enable_psci_bp_hardening,

	},

#endif

	{

	}