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Commit 0beb2bd3 authored by Soren Brinkmann's avatar Soren Brinkmann Committed by Michal Simek
Browse files

ARM: zynq: PM: Enable DDR clock stop 



The DDR controller can detect idle periods and leverage low power
features clock stop. When new requests occur, the DDRC resumes
normal operation.

Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 36ad5ae6

arch/arm/mach-zynq/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
#



# Common support

obj-y				:= common.o slcr.o

obj-y				:= common.o slcr.o pm.o

CFLAGS_REMOVE_hotplug.o		=-march=armv6k

CFLAGS_hotplug.o 		=-Wa,-march=armv7-a -mcpu=cortex-a9

obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o

arch/arm/mach-zynq/common.c

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ static int __init zynq_get_revision(void) 
static void __init zynq_init_late(void)

{

	zynq_core_pm_init();

	zynq_pm_late_init();

}



/**

arch/arm/mach-zynq/common.h

+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ extern void __iomem *zynq_scu_base; 
/* Hotplug */

extern void zynq_platform_cpu_die(unsigned int cpu);



void zynq_pm_late_init(void);



static inline void zynq_core_pm_init(void)

{

	/* A9 clock gating */

arch/arm/mach-zynq/pm.c

0 → 100644
+83 −0
Original line number Diff line number Diff line 
/*

 * Zynq power management

 *

 *  Copyright (C) 2012 - 2014 Xilinx

 *

 *  Sören Brinkmann <soren.brinkmann@xilinx.com>

 *

 * This program is free software: you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/io.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include "common.h"



/* register offsets */

#define DDRC_CTRL_REG1_OFFS		0x60

#define DDRC_DRAM_PARAM_REG3_OFFS	0x20



/* bitfields */

#define DDRC_CLOCKSTOP_MASK	BIT(23)

#define DDRC_SELFREFRESH_MASK	BIT(12)



static void __iomem *ddrc_base;



/**

 * zynq_pm_ioremap() - Create IO mappings

 * @comp:	DT compatible string

 * Return: Pointer to the mapped memory or NULL.

 *

 * Remap the memory region for a compatible DT node.

 */

static void __iomem *zynq_pm_ioremap(const char *comp)

{

	struct device_node *np;

	void __iomem *base = NULL;



	np = of_find_compatible_node(NULL, NULL, comp);

	if (np) {

		base = of_iomap(np, 0);

		of_node_put(np);

	} else {

		pr_warn("%s: no compatible node found for '%s'\n", __func__,

				comp);

	}



	return base;

}



/**

 * zynq_pm_late_init() - Power management init

 *

 * Initialization of power management related featurs and infrastructure.

 */

void __init zynq_pm_late_init(void)

{

	u32 reg;



	ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05");

	if (!ddrc_base) {

		pr_warn("%s: Unable to map DDRC IO memory.\n", __func__);

	} else {

		/*

		 * Enable DDRC clock stop feature. The HW takes care of

		 * entering/exiting the correct mode depending

		 * on activity state.

		 */

		reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);

		reg |= DDRC_CLOCKSTOP_MASK;

		writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);

	}

}