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Commit 0afb0e4e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: msm: Enable DCC V2 for sdm670 32 bit"

parents fbb4f92b 4cdfd282

arch/arm/configs/sdm670-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -498,6 +498,7 @@ CONFIG_MSM_CDSP_LOADER=y 
CONFIG_QCOM_SMCINVOKE=y

CONFIG_MSM_EVENT_TIMER=y

CONFIG_MSM_QBT1000=y

CONFIG_QCOM_DCC_V2=y

CONFIG_QTI_RPM_STATS_LOG=y

CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y

CONFIG_QMP_DEBUGFS_CLIENT=y

arch/arm/configs/sdm670_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -520,6 +520,7 @@ CONFIG_MSM_CDSP_LOADER=y 
CONFIG_QCOM_SMCINVOKE=y

CONFIG_MSM_EVENT_TIMER=y

CONFIG_MSM_QBT1000=y

CONFIG_QCOM_DCC_V2=y

CONFIG_QTI_RPM_STATS_LOG=y

CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y

CONFIG_QMP_DEBUGFS_CLIENT=y

drivers/soc/qcom/dcc_v2.c

+26 −3
Original line number Diff line number Diff line
@@ -162,6 +162,28 @@ static int dcc_sram_writel(struct dcc_drvdata *drvdata, 
	return 0;

}



static void dcc_sram_memset(const struct device *dev, void __iomem *dst,

			    int c, size_t count)

{

	u64 qc = (u8)c;



	qc |= qc << 8;

	qc |= qc << 16;



	if (!count || !IS_ALIGNED((unsigned long)dst, 4)

	    || !IS_ALIGNED((unsigned long)count, 4)) {

		dev_err(dev,

			"Target address or size not aligned with 4 bytes");

		return;

	}



	while (count >= 4) {

		__raw_writel_no_log(qc, dst);

		dst += 4;

		count -= 4;

	}

}



static bool dcc_ready(struct dcc_drvdata *drvdata)

{

	uint32_t val;
@@ -529,7 +551,7 @@ static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) 
	return 0;

overstep:

	ret = -EINVAL;

	memset_io(drvdata->ram_base, 0, drvdata->ram_size);

	dcc_sram_memset(drvdata->dev, drvdata->ram_base, 0, drvdata->ram_size);

	dev_err(drvdata->dev, "DCC SRAM oversteps, 0x%x (0x%x)\n",

		sram_offset, drvdata->ram_size);

err:
@@ -587,7 +609,8 @@ static int dcc_enable(struct dcc_drvdata *drvdata) 


	mutex_lock(&drvdata->mutex);



	memset_io(drvdata->ram_base, 0xDE, drvdata->ram_size);

	dcc_sram_memset(drvdata->dev, drvdata->ram_base, 0xDE,

			drvdata->ram_size);



	for (list = 0; list < DCC_MAX_LINK_LIST; list++) {
@@ -1647,7 +1670,7 @@ static int dcc_probe(struct platform_device *pdev) 
		drvdata->nr_config[i] = 0;

	}



	memset_io(drvdata->ram_base, 0, drvdata->ram_size);

	dcc_sram_memset(drvdata->dev, drvdata->ram_base, 0, drvdata->ram_size);



	drvdata->data_sink = DCC_DATA_SINK_SRAM;

	ret = of_property_read_string(pdev->dev.of_node, "qcom,data-sink",