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Commit 0ab0b6d2 authored by Abhilash Kesavan's avatar Abhilash Kesavan Committed by Kukjin Kim
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ARM: S3C64XX: Add support for Compact Flash driver on SMDK6410 



Following is added for the CF-ATA driver:
	- Platform data strucure instantiation
	- Platform device enabling code
	- Addition of cfcon clock
	- Platform-specific gpio setup code

Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: default avatarThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent db90005b

arch/arm/mach-s3c64xx/Kconfig

+7 −0
Original line number Original line Diff line number Diff line
@@ -57,6 +57,11 @@ config S3C64XX_SETUP_I2C1 
	help

	help

	  Common setup code for i2c bus 1.

	  Common setup code for i2c bus 1.





config S3C64XX_SETUP_IDE

	bool

	help

	  Common setup code for S3C64XX IDE.



config S3C64XX_SETUP_FB_24BPP

config S3C64XX_SETUP_FB_24BPP

	bool

	bool

	help

	help
@@ -95,6 +100,7 @@ config MACH_SMDK6410 
	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC

	select S3C_DEV_HSMMC1

	select S3C_DEV_HSMMC1

	select S3C_DEV_I2C1

	select S3C_DEV_I2C1

	select SAMSUNG_DEV_IDE

	select S3C_DEV_FB

	select S3C_DEV_FB

	select SAMSUNG_DEV_TS

	select SAMSUNG_DEV_TS

	select S3C_DEV_USB_HOST

	select S3C_DEV_USB_HOST
@@ -103,6 +109,7 @@ config MACH_SMDK6410 
	select HAVE_S3C2410_WATCHDOG

	select HAVE_S3C2410_WATCHDOG

	select S3C64XX_SETUP_SDHCI

	select S3C64XX_SETUP_SDHCI

	select S3C64XX_SETUP_I2C1

	select S3C64XX_SETUP_I2C1

	select S3C64XX_SETUP_IDE

	select S3C64XX_SETUP_FB_24BPP

	select S3C64XX_SETUP_FB_24BPP

	help

	help

	  Machine support for the Samsung SMDK6410

	  Machine support for the Samsung SMDK6410

arch/arm/mach-s3c64xx/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -35,6 +35,7 @@ obj-$(CONFIG_S3C64XX_DMA) += dma.o 




obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o

obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o

obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o

obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o

obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o

obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o

obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o

obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o

obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o

obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o

obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o

arch/arm/mach-s3c64xx/clock.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -310,6 +310,12 @@ static struct clk init_clocks[] = { 
		.id		= -1,

		.id		= -1,

		.parent		= &clk_p,

		.parent		= &clk_p,

		.ctrlbit	= S3C_CLKCON_PCLK_AC97,

		.ctrlbit	= S3C_CLKCON_PCLK_AC97,

	}, {

		.name		= "cfcon",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c64xx_hclk_ctrl,

		.ctrlbit	= S3C_CLKCON_HCLK_IHOST,

	}

	}

};

};

arch/arm/mach-s3c64xx/include/mach/map.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -86,6 +86,9 @@ 
#define S3C64XX_SZ_GPIO		SZ_4K

#define S3C64XX_SZ_GPIO		SZ_4K





#define S3C64XX_PA_SDRAM	(0x50000000)

#define S3C64XX_PA_SDRAM	(0x50000000)



#define S3C64XX_PA_CFCON	(0x70300000)



#define S3C64XX_PA_VIC0		(0x71200000)

#define S3C64XX_PA_VIC0		(0x71200000)

#define S3C64XX_PA_VIC1		(0x71300000)

#define S3C64XX_PA_VIC1		(0x71300000)
@@ -120,5 +123,6 @@ 
#define S3C_PA_WDT		S3C64XX_PA_WATCHDOG

#define S3C_PA_WDT		S3C64XX_PA_WATCHDOG





#define SAMSUNG_PA_ADC		S3C64XX_PA_ADC

#define SAMSUNG_PA_ADC		S3C64XX_PA_ADC

#define SAMSUNG_PA_CFCON	S3C64XX_PA_CFCON





#endif /* __ASM_ARCH_6400_MAP_H */
 
#endif /* __ASM_ARCH_6400_MAP_H */

arch/arm/mach-s3c64xx/include/mach/regs-clock.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -34,6 +34,7 @@ 
#define S3C_SCLK_GATE		S3C_CLKREG(0x38)

#define S3C_SCLK_GATE		S3C_CLKREG(0x38)

#define S3C_MEM0_GATE		S3C_CLKREG(0x3C)

#define S3C_MEM0_GATE		S3C_CLKREG(0x3C)

#define S3C6410_CLK_SRC2	S3C_CLKREG(0x10C)

#define S3C6410_CLK_SRC2	S3C_CLKREG(0x10C)

#define S3C_MEM_SYS_CFG		S3C_CLKREG(0x120)





/* CLKDIV0 */

/* CLKDIV0 */

#define S3C6400_CLKDIV0_PCLK_MASK	(0xf << 12)

#define S3C6400_CLKDIV0_PCLK_MASK	(0xf << 12)
@@ -154,4 +155,8 @@ 
#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT	(2)

#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT	(2)

#define S3C6400_CLKSRC_MFC		(1 << 4)

#define S3C6400_CLKSRC_MFC		(1 << 4)





/* MEM_SYS_CFG */

#define MEM_SYS_CFG_INDEP_CF		0x4000

#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON	0x30



#endif /* _PLAT_REGS_CLOCK_H */
 
#endif /* _PLAT_REGS_CLOCK_H */