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Commit 0a9cafb1 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: gcc-sdm845: Remove references for gcc_rx3_modem_clkref_clk 



The gcc_rx3_modem_clkref_clk clock will be controlled by modem on
SDM845. Remove support for it from the HLOS clock driver.

Change-Id: I5709bc8f25e754ed186c5dc42bbd5173ebcd2e7a
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent e4e90297

drivers/clk/qcom/gcc-sdm845.c

+0 −14
Original line number Diff line number Diff line
@@ -2450,19 +2450,6 @@ static struct clk_branch gcc_rx2_qlink_clkref_clk = { 
	},

};



static struct clk_branch gcc_rx3_modem_clkref_clk = {

	.halt_reg = 0x8c01c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c01c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_rx3_modem_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_sdcc2_ahb_clk = {

	.halt_reg = 0x14008,

	.halt_check = BRANCH_HALT,
@@ -3244,7 +3231,6 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { 
	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,

	[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,

	[GCC_RX2_QLINK_CLKREF_CLK] = &gcc_rx2_qlink_clkref_clk.clkr,

	[GCC_RX3_MODEM_CLKREF_CLK] = &gcc_rx3_modem_clkref_clk.clkr,

	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,

	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,

	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,

include/dt-bindings/clock/qcom,gcc-sdm845.h

+66 −67
Original line number Diff line number Diff line
@@ -124,73 +124,72 @@ 
#define GCC_QUPV3_WRAP_1_S_AHB_CLK				106

#define GCC_RX1_USB2_CLKREF_CLK					107

#define GCC_RX2_QLINK_CLKREF_CLK				108

#define GCC_RX3_MODEM_CLKREF_CLK				109

#define GCC_SDCC2_AHB_CLK					110

#define GCC_SDCC2_APPS_CLK					111

#define GCC_SDCC2_APPS_CLK_SRC					112

#define GCC_SDCC4_AHB_CLK					113

#define GCC_SDCC4_APPS_CLK					114

#define GCC_SDCC4_APPS_CLK_SRC					115

#define GCC_SYS_NOC_CPUSS_AHB_CLK				116

#define GCC_TSIF_AHB_CLK					117

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				118

#define GCC_TSIF_REF_CLK					119

#define GCC_TSIF_REF_CLK_SRC					120

#define GCC_UFS_CARD_AHB_CLK					121

#define GCC_UFS_CARD_AXI_CLK					122

#define GCC_UFS_CARD_AXI_CLK_SRC				123

#define GCC_UFS_CARD_CLKREF_CLK					124

#define GCC_UFS_CARD_ICE_CORE_CLK				125

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				126

#define GCC_UFS_CARD_PHY_AUX_CLK				127

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				128

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				129

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				130

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				131

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				132

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			133

#define GCC_UFS_MEM_CLKREF_CLK					134

#define GCC_UFS_PHY_AHB_CLK					135

#define GCC_UFS_PHY_AXI_CLK					136

#define GCC_UFS_PHY_AXI_CLK_SRC					137

#define GCC_UFS_PHY_ICE_CORE_CLK				138

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				139

#define GCC_UFS_PHY_PHY_AUX_CLK					140

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				141

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				142

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				143

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				144

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				145

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				146

#define GCC_USB30_PRIM_MASTER_CLK				147

#define GCC_USB30_PRIM_MASTER_CLK_SRC				148

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				149

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			150

#define GCC_USB30_PRIM_SLEEP_CLK				151

#define GCC_USB30_SEC_MASTER_CLK				152

#define GCC_USB30_SEC_MASTER_CLK_SRC				153

#define GCC_USB30_SEC_MOCK_UTMI_CLK				154

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				155

#define GCC_USB30_SEC_SLEEP_CLK					156

#define GCC_USB3_PRIM_CLKREF_CLK				157

#define GCC_USB3_PRIM_PHY_AUX_CLK				158

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				159

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				160

#define GCC_USB3_PRIM_PHY_PIPE_CLK				161

#define GCC_USB3_SEC_CLKREF_CLK					162

#define GCC_USB3_SEC_PHY_AUX_CLK				163

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				164

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				165

#define GCC_USB3_SEC_PHY_PIPE_CLK				166

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				167

#define GCC_VIDEO_AHB_CLK					168

#define GCC_VIDEO_AXI_CLK					169

#define GCC_VIDEO_XO_CLK					170

#define GPLL0							171

#define GPLL0_OUT_EVEN						172

#define GPLL0_OUT_MAIN						173

#define GPLL1							174

#define GPLL1_OUT_MAIN						175

#define GCC_SDCC2_AHB_CLK					109

#define GCC_SDCC2_APPS_CLK					110

#define GCC_SDCC2_APPS_CLK_SRC					111

#define GCC_SDCC4_AHB_CLK					112

#define GCC_SDCC4_APPS_CLK					113

#define GCC_SDCC4_APPS_CLK_SRC					114

#define GCC_SYS_NOC_CPUSS_AHB_CLK				115

#define GCC_TSIF_AHB_CLK					116

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				117

#define GCC_TSIF_REF_CLK					118

#define GCC_TSIF_REF_CLK_SRC					119

#define GCC_UFS_CARD_AHB_CLK					120

#define GCC_UFS_CARD_AXI_CLK					121

#define GCC_UFS_CARD_AXI_CLK_SRC				122

#define GCC_UFS_CARD_CLKREF_CLK					123

#define GCC_UFS_CARD_ICE_CORE_CLK				124

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				125

#define GCC_UFS_CARD_PHY_AUX_CLK				126

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				127

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				128

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				129

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				130

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				131

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			132

#define GCC_UFS_MEM_CLKREF_CLK					133

#define GCC_UFS_PHY_AHB_CLK					134

#define GCC_UFS_PHY_AXI_CLK					135

#define GCC_UFS_PHY_AXI_CLK_SRC					136

#define GCC_UFS_PHY_ICE_CORE_CLK				137

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				138

#define GCC_UFS_PHY_PHY_AUX_CLK					139

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				140

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				141

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				142

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				143

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				144

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				145

#define GCC_USB30_PRIM_MASTER_CLK				146

#define GCC_USB30_PRIM_MASTER_CLK_SRC				147

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				148

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			149

#define GCC_USB30_PRIM_SLEEP_CLK				150

#define GCC_USB30_SEC_MASTER_CLK				151

#define GCC_USB30_SEC_MASTER_CLK_SRC				152

#define GCC_USB30_SEC_MOCK_UTMI_CLK				153

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				154

#define GCC_USB30_SEC_SLEEP_CLK					155

#define GCC_USB3_PRIM_CLKREF_CLK				156

#define GCC_USB3_PRIM_PHY_AUX_CLK				157

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				158

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				159

#define GCC_USB3_PRIM_PHY_PIPE_CLK				160

#define GCC_USB3_SEC_CLKREF_CLK					161

#define GCC_USB3_SEC_PHY_AUX_CLK				162

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				163

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				164

#define GCC_USB3_SEC_PHY_PIPE_CLK				165

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				166

#define GCC_VIDEO_AHB_CLK					167

#define GCC_VIDEO_AXI_CLK					168

#define GCC_VIDEO_XO_CLK					169

#define GPLL0							170

#define GPLL0_OUT_EVEN						171

#define GPLL0_OUT_MAIN						172

#define GPLL1							173

#define GPLL1_OUT_MAIN						174



/* GCC reset clocks */

#define GCC_GPU_BCR						0