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Commit 09e3b8fa authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add DT node for aop-qmp clock controller on SDM845 v2"

parents 9d52f3ec 0836d18d

Documentation/devicetree/bindings/clock/qcom,aop-qmp.txt

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. Always On Processor Clock controller Binding 
------------------------------------------------------------------------



Required properties :

- compatible : must be "qcom,aop-qmp-clk"

- compatible : must be "qcom,aop-qmp-clk-v1" or "qcom,aop-qmp-clk-v2".

- #clock-cells : must contain 1

- mboxes : list of QMP mailbox phandle and channel identifier tuples.

- mbox-names: List of identifier strings for each mailbox channel.
@@ -10,7 +10,7 @@ Required properties : 


Example :

	clock_qdss: qcom,aopclk {

		compatible = "qcom,aop-qmp-clk";

		compatible = "qcom,aop-qmp-clk-v1";

		#clock-cells = <1>;

		mboxes = <&qmp_aop 0>;

		mbox-names = "qdss_clk";

arch/arm64/boot/dts/qcom/sdm845-v2.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -570,6 +570,10 @@ 
	compatible = "qcom,video_cc-sdm845-v2";

};



&clock_aop {

	compatible = "qcom,aop-qmp-clk-v2";

};



&msm_vidc {

	qcom,allowed-clock-rates = <100000000 200000000 330000000

		404000000 444000000 533000000>;

arch/arm64/boot/dts/qcom/sdm845.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1402,7 +1402,7 @@ 
	};



	clock_aop: qcom,aopclk {

		compatible = "qcom,aop-qmp-clk";

		compatible = "qcom,aop-qmp-clk-v1";

		#clock-cells = <1>;

		mboxes = <&qmp_aop 0>;

		mbox-names = "qdss_clk";

drivers/clk/qcom/clk-aop-qmp.c

+33 −11
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ struct qmp_pkt { 
	void *data;

};



#define DEFINE_CLK_AOP_QMP(_name, _class, _res, _estate, _dstate)	\

#define DEFINE_CLK_AOP_QMP(_name, _class, _res, _estate, _dstate, _flags) \

	static struct clk_aop_qmp _name = {				\

		.msg.class = #_class,					\

		.msg.res = #_res,					\
@@ -40,7 +40,7 @@ struct qmp_pkt { 
			.ops = &aop_qmp_clk_ops,			\

			.name = #_name,					\

			.num_parents = 0,				\

			.flags = CLK_ENABLE_HAND_OFF,			\

			.flags = _flags,				\

		},							\

	}
@@ -214,13 +214,25 @@ static const struct clk_ops aop_qmp_clk_ops = { 
	.is_enabled	= clk_aop_qmp_is_enabled,

};



DEFINE_CLK_AOP_QMP(qdss_qmp_clk, clock, qdss,

		QDSS_CLK_LEVEL_DYNAMIC, QDSS_CLK_LEVEL_OFF);

DEFINE_CLK_AOP_QMP(qdss_qmp_clk, clock, qdss, QDSS_CLK_LEVEL_DYNAMIC,

			QDSS_CLK_LEVEL_OFF, CLK_ENABLE_HAND_OFF);

DEFINE_CLK_AOP_QMP(qdss_ao_qmp_clk, clock, qdss_ao, QDSS_CLK_LEVEL_DYNAMIC,

			QDSS_CLK_LEVEL_OFF, 0);



static struct clk_hw *aop_qmp_clk_hws[] = {

	[QDSS_CLK] = &qdss_qmp_clk.hw,

	[QDSS_AO_CLK] = &qdss_ao_qmp_clk.hw,

};



/*

 * Due to HW limitations on v1, the qdss_ao clock was not supported by the clock

 * driver on AOP.

 */

static void aop_qmp_fixup_v1(void)

{

	aop_qmp_clk_hws[QDSS_AO_CLK] = NULL;

}



static int qmp_update_client(struct clk_hw *hw, struct device *dev,

		struct mbox_chan *mbox)

{
@@ -250,7 +262,7 @@ static int qmp_update_client(struct clk_hw *hw, struct device *dev, 


static int aop_qmp_clk_probe(struct platform_device *pdev)

{

	struct clk *clk;

	struct clk *clk = NULL;

	struct device_node *np = pdev->dev.of_node;

	struct mbox_chan *mbox = NULL;

	int num_clks = ARRAY_SIZE(aop_qmp_clk_hws);
@@ -264,7 +276,12 @@ static int aop_qmp_clk_probe(struct platform_device *pdev) 
	if (ret < 0)

		return ret;



	if (of_device_is_compatible(pdev->dev.of_node, "qcom,aop-qmp-clk-v1"))

		aop_qmp_fixup_v1();



	for (i = 1; i < num_clks; i++) {

		if (!aop_qmp_clk_hws[i])

			continue;

		ret = qmp_update_client(aop_qmp_clk_hws[i], &pdev->dev, mbox);

		if (ret < 0) {

			dev_err(&pdev->dev, "Failed to update QMP client %d\n",
@@ -273,13 +290,17 @@ static int aop_qmp_clk_probe(struct platform_device *pdev) 
		}

	}



	for (i = 0; i < num_clks; i++) {

		ret = clk_aop_qmp_prepare(aop_qmp_clk_hws[i]);

	/*

	 * Proxy vote on the QDSS clock. This is needed to avoid issues with

	 * excessive requests on the QMP layer during the QDSS driver probe.

	 */

	ret = clk_aop_qmp_prepare(&qdss_qmp_clk.hw);

	if (ret < 0)

		goto fail;

	}



	for (i = 0; i < num_clks; i++) {

		if (!aop_qmp_clk_hws[i])

			continue;

		clk = devm_clk_register(&pdev->dev, aop_qmp_clk_hws[i]);

		if (IS_ERR(clk)) {

			ret = PTR_ERR(clk);
@@ -303,7 +324,8 @@ static int aop_qmp_clk_probe(struct platform_device *pdev) 
}



static const struct of_device_id aop_qmp_clk_of_match[] = {

	{ .compatible = "qcom,aop-qmp-clk", },

	{ .compatible = "qcom,aop-qmp-clk-v1" },

	{ .compatible = "qcom,aop-qmp-clk-v2" },

	{}

};

include/dt-bindings/clock/qcom,aop-qmp.h

+1 −1
Original line number Diff line number Diff line
@@ -25,5 +25,5 @@ 


/* clocks id */

#define QDSS_CLK			0



#define QDSS_AO_CLK			1

#endif