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Commit 09bf7fb0 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.9.201 into android-4.9-q 



Changes in 4.9.201
	CDC-NCM: handle incomplete transfer of MTU
	ipv4: Fix table id reference in fib_sync_down_addr
	net: fix data-race in neigh_event_send()
	net: usb: qmi_wwan: add support for DW5821e with eSIM support
	NFC: fdp: fix incorrect free object
	nfc: netlink: fix double device reference drop
	NFC: st21nfca: fix double free
	qede: fix NULL pointer deref in __qede_remove()
	ALSA: timer: Fix incorrectly assigned timer instance
	ALSA: bebob: fix to detect configured source of sampling clock for Focusrite Saffire Pro i/o series
	ALSA: hda/ca0132 - Fix possible workqueue stall
	mm: thp: handle page cache THP correctly in PageTransCompoundMap
	mm, vmstat: hide /proc/pagetypeinfo from normal users
	dump_stack: avoid the livelock of the dump_lock
	perf tools: Fix time sorting
	drm/radeon: fix si_enable_smc_cac() failed issue
	ceph: fix use-after-free in __ceph_remove_cap()
	iio: imu: adis16480: make sure provided frequency is positive
	netfilter: nf_tables: Align nft_expr private data to 64-bit
	netfilter: ipset: Fix an error code in ip_set_sockfn_get()
	can: usb_8dev: fix use-after-free on disconnect
	can: c_can: c_can_poll(): only read status register after status IRQ
	can: peak_usb: fix a potential out-of-sync while decoding packets
	can: gs_usb: gs_can_open(): prevent memory leak
	can: peak_usb: fix slab info leak
	configfs: Fix bool initialization/comparison
	configfs: stash the data we need into configfs_buffer at open time
	configfs_register_group() shouldn't be (and isn't) called in rmdirable parts
	configfs: new object reprsenting tree fragments
	configfs: provide exclusion between IO and removals
	configfs: fix a deadlock in configfs_symlink()
	usbip: stub_rx: fix static checker warning on unnecessary checks
	usbip: Fix vhci_urb_enqueue() URB null transfer buffer error path
	usbip: fix possibility of dereference by NULLL pointer in vhci_hcd.c
	drivers: usb: usbip: Add missing break statement to switch
	PCI: tegra: Enable Relaxed Ordering only for Tegra20 & Tegra30
	dmaengine: xilinx_dma: Fix control reg update in vdma_channel_set_config
	HID: intel-ish-hid: fix wrong error handling in ishtp_cl_alloc_tx_ring()
	scsi: qla2xxx: fixup incorrect usage of host_byte
	scsi: lpfc: Honor module parameter lpfc_use_adisc
	ipvs: move old_secure_tcp into struct netns_ipvs
	bonding: fix unexpected IFF_BONDING bit unset
	usb: fsl: Check memory resource before releasing it
	usb: gadget: udc: atmel: Fix interrupt storm in FIFO mode.
	usb: gadget: composite: Fix possible double free memory bug
	usb: gadget: configfs: fix concurrent issue between composite APIs
	usb: dwc3: remove the call trace of USBx_GFLADJ
	perf/x86/amd/ibs: Fix reading of the IBS OpData register and thus precise RIP validity
	perf/x86/amd/ibs: Handle erratum #420 only on the affected CPU family (10h)
	USB: Skip endpoints with 0 maxpacket length
	RDMA/iw_cxgb4: Avoid freeing skb twice in arp failure case
	scsi: qla2xxx: stop timer in shutdown path
	fjes: Handle workqueue allocation failure
	net: hisilicon: Fix "Trying to free already-free IRQ"
	NFSv4: Don't allow a cached open with a revoked delegation
	net: ethernet: arc: add the missed clk_disable_unprepare
	igb: Fix constant media auto sense switching when no cable is connected
	e1000: fix memory leaks
	x86/apic: Move pending interrupt check code into it's own function
	x86/apic: Drop logical_smp_processor_id() inline
	x86/apic/32: Avoid bogus LDR warnings
	can: flexcan: disable completely the ECC mechanism
	mm/filemap.c: don't initiate writeback if mapping has no dirty pages
	cgroup,writeback: don't switch wbs immediately on dead wbs if the memcg is dead
	net: prevent load/store tearing on sk->sk_stamp
	drm/i915: kick out cmd_parser specific structs from i915_drv.h
	drm/i915: cleanup use of INSTR_CLIENT_MASK
	drm/i915: return EACCES for check_cmd() failures
	drm/i915: don't whitelist oacontrol in cmd parser
	drm/i915: Use the precomputed value for whether to enable command parsing
	drm/i915/cmdparser: Limit clflush to active cachelines
	drm/i915/gtt: Add read only pages to gen8_pte_encode
	drm/i915/gtt: Read-only pages for insert_entries on bdw+
	drm/i915/gtt: Disable read-only support under GVT
	drm/i915: Prevent writing into a read-only object via a GGTT mmap
	drm/i915/cmdparser: Check reg_table_count before derefencing.
	drm/i915/cmdparser: Do not check past the cmd length.
	drm/i915: Silence smatch for cmdparser
	drm/i915: Move engine->needs_cmd_parser to engine->flags
	drm/i915: Rename gen7 cmdparser tables
	drm/i915: Disable Secure Batches for gen6+
	drm/i915: Remove Master tables from cmdparser
	drm/i915: Add support for mandatory cmdparsing
	drm/i915: Support ro ppgtt mapped cmdparser shadow buffers
	drm/i915: Allow parsing of unsized batches
	drm/i915: Add gen9 BCS cmdparsing
	drm/i915/cmdparser: Use explicit goto for error paths
	drm/i915/cmdparser: Add support for backward jumps
	drm/i915/cmdparser: Ignore Length operands during command matching
	drm/i915: Lower RM timeout to avoid DSI hard hangs
	drm/i915/gen8+: Add RC6 CTX corruption WA
	drm/i915/cmdparser: Fix jump whitelist clearing
	Linux 4.9.201

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents 851ba64a 9829ecfd

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 9

SUBLEVEL = 200

SUBLEVEL = 201

EXTRAVERSION =

NAME = Roaring Lionus

arch/x86/events/amd/ibs.c

+5 −3
Original line number Diff line number Diff line
@@ -388,6 +388,7 @@ static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs, 
					  struct hw_perf_event *hwc, u64 config)

{

	config &= ~perf_ibs->cnt_mask;

	if (boot_cpu_data.x86 == 0x10)

		wrmsrl(hwc->config_base, config);

	config &= ~perf_ibs->enable_mask;

	wrmsrl(hwc->config_base, config);
@@ -563,7 +564,8 @@ static struct perf_ibs perf_ibs_op = { 
	},

	.msr			= MSR_AMD64_IBSOPCTL,

	.config_mask		= IBS_OP_CONFIG_MASK,

	.cnt_mask		= IBS_OP_MAX_CNT,

	.cnt_mask		= IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |

				  IBS_OP_CUR_CNT_RAND,

	.enable_mask		= IBS_OP_ENABLE,

	.valid_mask		= IBS_OP_VAL,

	.max_period		= IBS_OP_MAX_CNT << 4,
@@ -624,7 +626,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) 
	if (event->attr.sample_type & PERF_SAMPLE_RAW)

		offset_max = perf_ibs->offset_max;

	else if (check_rip)

		offset_max = 2;

		offset_max = 3;

	else

		offset_max = 1;

	do {

arch/x86/include/asm/smp.h

+0 −10
Original line number Diff line number Diff line
@@ -177,16 +177,6 @@ extern int safe_smp_processor_id(void); 
#endif



#ifdef CONFIG_X86_LOCAL_APIC



#ifndef CONFIG_X86_64

static inline int logical_smp_processor_id(void)

{

	/* we don't want to mark this access volatile - bad code generation */

	return GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));

}



#endif



extern int hard_smp_processor_id(void);



#else /* CONFIG_X86_LOCAL_APIC */

arch/x86/kernel/apic/apic.c

+67 −55
Original line number Diff line number Diff line
@@ -1281,6 +1281,56 @@ static void lapic_setup_esr(void) 
			oldvalue, value);

}



static void apic_pending_intr_clear(void)

{

	long long max_loops = cpu_khz ? cpu_khz : 1000000;

	unsigned long long tsc = 0, ntsc;

	unsigned int value, queued;

	int i, j, acked = 0;



	if (boot_cpu_has(X86_FEATURE_TSC))

		tsc = rdtsc();

	/*

	 * After a crash, we no longer service the interrupts and a pending

	 * interrupt from previous kernel might still have ISR bit set.

	 *

	 * Most probably by now CPU has serviced that pending interrupt and

	 * it might not have done the ack_APIC_irq() because it thought,

	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it

	 * does not clear the ISR bit and cpu thinks it has already serivced

	 * the interrupt. Hence a vector might get locked. It was noticed

	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.

	 */

	do {

		queued = 0;

		for (i = APIC_ISR_NR - 1; i >= 0; i--)

			queued |= apic_read(APIC_IRR + i*0x10);



		for (i = APIC_ISR_NR - 1; i >= 0; i--) {

			value = apic_read(APIC_ISR + i*0x10);

			for (j = 31; j >= 0; j--) {

				if (value & (1<<j)) {

					ack_APIC_irq();

					acked++;

				}

			}

		}

		if (acked > 256) {

			printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",

			       acked);

			break;

		}

		if (queued) {

			if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {

				ntsc = rdtsc();

				max_loops = (cpu_khz << 10) - (ntsc - tsc);

			} else

				max_loops--;

		}

	} while (queued && max_loops > 0);

	WARN_ON(max_loops <= 0);

}



/**

 * setup_local_APIC - setup the local APIC

 *
@@ -1290,13 +1340,8 @@ static void lapic_setup_esr(void) 
void setup_local_APIC(void)

{

	int cpu = smp_processor_id();

	unsigned int value, queued;

	int i, j, acked = 0;

	unsigned long long tsc = 0, ntsc;

	long long max_loops = cpu_khz ? cpu_khz : 1000000;

	unsigned int value;



	if (boot_cpu_has(X86_FEATURE_TSC))

		tsc = rdtsc();



	if (disable_apic) {

		disable_ioapic_support();
@@ -1336,16 +1381,21 @@ void setup_local_APIC(void) 
	apic->init_apic_ldr();



#ifdef CONFIG_X86_32

	if (apic->dest_logical) {

		int logical_apicid, ldr_apicid;



		/*

		 * APIC LDR is initialized.  If logical_apicid mapping was

	 * initialized during get_smp_config(), make sure it matches the

	 * actual value.

		 * initialized during get_smp_config(), make sure it matches

		 * the actual value.

		 */

	i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);

	WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());

	/* always use the value from LDR */

	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =

		logical_smp_processor_id();

		logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);

		ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));

		if (logical_apicid != BAD_APICID)

			WARN_ON(logical_apicid != ldr_apicid);

		/* Always use the value from LDR. */

		early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;

	}

#endif



	/*
@@ -1356,45 +1406,7 @@ void setup_local_APIC(void) 
	value &= ~APIC_TPRI_MASK;

	apic_write(APIC_TASKPRI, value);



	/*

	 * After a crash, we no longer service the interrupts and a pending

	 * interrupt from previous kernel might still have ISR bit set.

	 *

	 * Most probably by now CPU has serviced that pending interrupt and

	 * it might not have done the ack_APIC_irq() because it thought,

	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it

	 * does not clear the ISR bit and cpu thinks it has already serivced

	 * the interrupt. Hence a vector might get locked. It was noticed

	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.

	 */

	do {

		queued = 0;

		for (i = APIC_ISR_NR - 1; i >= 0; i--)

			queued |= apic_read(APIC_IRR + i*0x10);



		for (i = APIC_ISR_NR - 1; i >= 0; i--) {

			value = apic_read(APIC_ISR + i*0x10);

			for (j = 31; j >= 0; j--) {

				if (value & (1<<j)) {

					ack_APIC_irq();

					acked++;

				}

			}

		}

		if (acked > 256) {

			printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",

			       acked);

			break;

		}

		if (queued) {

			if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {

				ntsc = rdtsc();

				max_loops = (cpu_khz << 10) - (ntsc - tsc);

			} else

				max_loops--;

		}

	} while (queued && max_loops > 0);

	WARN_ON(max_loops <= 0);

	apic_pending_intr_clear();



	/*

	 * Now that we are all set up, enable the APIC

drivers/dma/xilinx/xilinx_dma.c

+7 −0
Original line number Diff line number Diff line
@@ -72,6 +72,9 @@ 
#define XILINX_DMA_DMACR_CIRC_EN		BIT(1)

#define XILINX_DMA_DMACR_RUNSTOP		BIT(0)

#define XILINX_DMA_DMACR_FSYNCSRC_MASK		GENMASK(6, 5)

#define XILINX_DMA_DMACR_DELAY_MASK		GENMASK(31, 24)

#define XILINX_DMA_DMACR_FRAME_COUNT_MASK	GENMASK(23, 16)

#define XILINX_DMA_DMACR_MASTER_MASK		GENMASK(11, 8)



#define XILINX_DMA_REG_DMASR			0x0004

#define XILINX_DMA_DMASR_EOL_LATE_ERR		BIT(15)
@@ -2054,8 +2057,10 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan, 
	chan->config.gen_lock = cfg->gen_lock;

	chan->config.master = cfg->master;



	dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;

	if (cfg->gen_lock && chan->genlock) {

		dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;

		dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;

		dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;

	}
@@ -2069,11 +2074,13 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan, 
	chan->config.delay = cfg->delay;



	if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {

		dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;

		dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;

		chan->config.coalesc = cfg->coalesc;

	}



	if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {

		dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;

		dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;

		chan->config.delay = cfg->delay;

	}