Loading arch/arc/boot/dts/axc003.dtsi +7 −6 Original line number Diff line number Diff line Loading @@ -72,12 +72,13 @@ }; /* * This INTC is actually connected to DW APB GPIO * which acts as a wire between MB INTC and CPU INTC. * GPIO INTC is configured in platform init code * and here we mimic direct connection from MB INTC to * CPU INTC, thus we set "interrupts = <7>" instead of * "interrupts = <12>" * The DW APB ICTL intc on MB is connected to CPU intc via a * DT "invisible" DW APB GPIO block, configured to simply pass thru * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c) * * So here we mimic a direct connection betwen them, ignoring the * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core) * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO) * * This intc actually resides on MB, but we move it here to * avoid duplicating the MB dtsi file given that IRQ from Loading arch/arc/include/asm/cmpxchg.h +11 −11 Original line number Diff line number Diff line Loading @@ -110,18 +110,18 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, sizeof(*(ptr)))) /* * On ARC700, EX insn is inherently atomic, so by default "vanilla" xchg() need * not require any locking. However there's a quirk. * ARC lacks native CMPXCHG, thus emulated (see above), using external locking - * incidently it "reuses" the same atomic_ops_lock used by atomic APIs. * Now, llist code uses cmpxchg() and xchg() on same data, so xchg() needs to * abide by same serializing rules, thus ends up using atomic_ops_lock as well. * xchg() maps directly to ARC EX instruction which guarantees atomicity. * However in !LLSC config, it also needs to be use @atomic_ops_lock spinlock * due to a subtle reason: * - For !LLSC, cmpxchg() needs to use that lock (see above) and there is lot * of kernel code which calls xchg()/cmpxchg() on same data (see llist.h) * Hence xchg() needs to follow same locking rules. * * This however is only relevant if SMP and/or ARC lacks LLSC * if (UP or LLSC) * xchg doesn't need serialization * else <==> !(UP or LLSC) <==> (!UP and !LLSC) <==> (SMP and !LLSC) * xchg needs serialization * Technically the lock is also needed for UP (boils down to irq save/restore) * but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to * be disabled thus can't possibly be interrpted/preempted/clobbered by xchg() * Other way around, xchg is one instruction anyways, so can't be interrupted * as such */ #if !defined(CONFIG_ARC_HAS_LLSC) && defined(CONFIG_SMP) Loading arch/arc/include/asm/perf_event.h +1 −1 Original line number Diff line number Diff line Loading @@ -95,7 +95,7 @@ static const char * const arc_pmu_ev_hw_map[] = { /* counts condition */ [PERF_COUNT_HW_INSTRUCTIONS] = "iall", [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", /* Excludes ZOL jumps */ [PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */ [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */ Loading arch/arc/kernel/perf_event.c +2 −2 Original line number Diff line number Diff line Loading @@ -199,8 +199,8 @@ static void arc_pmu_start(struct perf_event *event, int flags) event->hw.state = 0; /* enable ARC pmu here */ write_aux_reg(ARC_REG_PCT_INDEX, idx); write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); write_aux_reg(ARC_REG_PCT_INDEX, idx); /* counter # */ write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */ } static void arc_pmu_stop(struct perf_event *event, int flags) Loading arch/arc/kernel/process.c +1 −1 Original line number Diff line number Diff line Loading @@ -65,7 +65,7 @@ asmlinkage void ret_from_fork(void); * ------------------ * | r25 | <==== top of Stack (thread.ksp) * ~ ~ * | --to-- | (CALLEE Regs of user mode) * | --to-- | (CALLEE Regs of kernel mode) * | r13 | * ------------------ * | fp | Loading Loading
arch/arc/boot/dts/axc003.dtsi +7 −6 Original line number Diff line number Diff line Loading @@ -72,12 +72,13 @@ }; /* * This INTC is actually connected to DW APB GPIO * which acts as a wire between MB INTC and CPU INTC. * GPIO INTC is configured in platform init code * and here we mimic direct connection from MB INTC to * CPU INTC, thus we set "interrupts = <7>" instead of * "interrupts = <12>" * The DW APB ICTL intc on MB is connected to CPU intc via a * DT "invisible" DW APB GPIO block, configured to simply pass thru * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c) * * So here we mimic a direct connection betwen them, ignoring the * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core) * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO) * * This intc actually resides on MB, but we move it here to * avoid duplicating the MB dtsi file given that IRQ from Loading
arch/arc/include/asm/cmpxchg.h +11 −11 Original line number Diff line number Diff line Loading @@ -110,18 +110,18 @@ static inline unsigned long __xchg(unsigned long val, volatile void *ptr, sizeof(*(ptr)))) /* * On ARC700, EX insn is inherently atomic, so by default "vanilla" xchg() need * not require any locking. However there's a quirk. * ARC lacks native CMPXCHG, thus emulated (see above), using external locking - * incidently it "reuses" the same atomic_ops_lock used by atomic APIs. * Now, llist code uses cmpxchg() and xchg() on same data, so xchg() needs to * abide by same serializing rules, thus ends up using atomic_ops_lock as well. * xchg() maps directly to ARC EX instruction which guarantees atomicity. * However in !LLSC config, it also needs to be use @atomic_ops_lock spinlock * due to a subtle reason: * - For !LLSC, cmpxchg() needs to use that lock (see above) and there is lot * of kernel code which calls xchg()/cmpxchg() on same data (see llist.h) * Hence xchg() needs to follow same locking rules. * * This however is only relevant if SMP and/or ARC lacks LLSC * if (UP or LLSC) * xchg doesn't need serialization * else <==> !(UP or LLSC) <==> (!UP and !LLSC) <==> (SMP and !LLSC) * xchg needs serialization * Technically the lock is also needed for UP (boils down to irq save/restore) * but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to * be disabled thus can't possibly be interrpted/preempted/clobbered by xchg() * Other way around, xchg is one instruction anyways, so can't be interrupted * as such */ #if !defined(CONFIG_ARC_HAS_LLSC) && defined(CONFIG_SMP) Loading
arch/arc/include/asm/perf_event.h +1 −1 Original line number Diff line number Diff line Loading @@ -95,7 +95,7 @@ static const char * const arc_pmu_ev_hw_map[] = { /* counts condition */ [PERF_COUNT_HW_INSTRUCTIONS] = "iall", [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", /* Excludes ZOL jumps */ [PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */ [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */ Loading
arch/arc/kernel/perf_event.c +2 −2 Original line number Diff line number Diff line Loading @@ -199,8 +199,8 @@ static void arc_pmu_start(struct perf_event *event, int flags) event->hw.state = 0; /* enable ARC pmu here */ write_aux_reg(ARC_REG_PCT_INDEX, idx); write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); write_aux_reg(ARC_REG_PCT_INDEX, idx); /* counter # */ write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */ } static void arc_pmu_stop(struct perf_event *event, int flags) Loading
arch/arc/kernel/process.c +1 −1 Original line number Diff line number Diff line Loading @@ -65,7 +65,7 @@ asmlinkage void ret_from_fork(void); * ------------------ * | r25 | <==== top of Stack (thread.ksp) * ~ ~ * | --to-- | (CALLEE Regs of user mode) * | --to-- | (CALLEE Regs of kernel mode) * | r13 | * ------------------ * | fp | Loading