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Commit 08d3caf2 authored by Sahitya Tummala's avatar Sahitya Tummala Committed by Xiaonian Wang
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mmc: sdhci-msm: get lower bus speed mode for clock scaling 



The lower bus speed mode to be used during clock scaling may
vary based on the target. Hence, add a new dtsi property to
define this bus speed mode.

Change-Id: If8e2d125b8246ca479f816a475940bb357138297
Signed-off-by: default avatarSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: default avatarAsutosh Das <asutoshd@codeaurora.org>
[xiaonian@codeaurora.org: fixed trivial merge conflicts]
Signed-off-by: default avatarXiaonian Wang <xiaonian@codeaurora.org>
parent a66b9ffd

Documentation/devicetree/bindings/mmc/sdhci-msm.txt

+6 −0
Original line number Diff line number Diff line
@@ -68,6 +68,10 @@ Optional Properties: 
	  command-queueing mode or legacy respectively.

	- qcom,core_3_0v_support: an optional property that is used to fake

	  3.0V support for SDIO devices.

	- qcom,scaling-lower-bus-speed-mode:	specifies the lower bus speed mode to be used

						during clock scaling. If this property is not

						defined, then it falls back to the default HS

						bus speed mode to maintain backward compatibility.



In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage).

	- qcom,<supply>-always-on - specifies whether supply should be kept "on" always.
@@ -130,6 +134,8 @@ Example: 
		qcom,large-address-bus;

		qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";



		qcom,scaling-lower-bus-speed-mode = "DDR52";



		gpios = <&msmgpio 40 0>, /* CLK */

			<&msmgpio 39 0>, /* CMD */

			<&msmgpio 38 0>, /* DATA0 */

drivers/mmc/host/sdhci-msm.c

+14 −0
Original line number Diff line number Diff line
@@ -1815,6 +1815,7 @@ struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev, 
	int clk_table_len;

	u32 *clk_table = NULL;

	enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW;

	const char *lower_bus_speed = NULL;



	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);

	if (!pdata) {
@@ -1845,6 +1846,19 @@ struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev, 
			!msm_host->mmc->clk_scaling.freq_table_sz)

			dev_err(dev, "bad dts clock scaling frequencies\n");



	/*

	 * Few hosts can support DDR52 mode at the same lower

	 * system voltage corner as high-speed mode. In such cases,

	 * it is always better to put it in DDR mode which will

	 * improve the performance without any power impact.

	 */

	if (!of_property_read_string(np, "qcom,scaling-lower-bus-speed-mode",

				&lower_bus_speed)) {

		if (!strcmp(lower_bus_speed, "DDR52"))

			msm_host->mmc->clk_scaling.lower_bus_speed_mode |=

				MMC_SCALING_LOWER_DDR52_MODE;

	}



	if (sdhci_msm_dt_get_array(dev, "qcom,clk-rates",

			&clk_table, &clk_table_len, 0)) {

		dev_err(dev, "failed parsing supported clock rates\n");