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Commit 0846697c authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915/chv: Implement WaDisableCSUnitClockGating:chv 



This workaround is listed for CHV, but not for BDW. However BSpec notes
that on BDW CSunit clock gating is always disabled irrespective of the
relevant bit in the GEN6_UGCTL1 registers. For CHV however, such text
is not present in BSpec, so it seems safer to just set the bit.

Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent acea6f95

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -5393,6 +5393,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev) 
	/* WaDisableSemaphoreAndSyncFlipWait:chv */

	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,

		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));



	/* WaDisableCSUnitClockGating:chv */

	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |

		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);

}



static void g4x_init_clock_gating(struct drm_device *dev)