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Commit 08247f7d authored by Narender Ankam's avatar Narender Ankam Committed by Gerrit - the friendly Code Review server
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drm/msm: add YUV422 format support 



Add DRM_MODE_FLAG_SUPPORTS_YUV422 flag to all EDID modes
if downstream device support YUV422 format.
Add support to configure CDM block to output YUV422 format.

Also capture max bits per channel supported for YUV420 modes.

Change-Id: I76bffbf9bf04267978bb364412d24b40ab845963
Signed-off-by: default avatarNarender Ankam <nankam@codeaurora.org>
Signed-off-by: default avatarChirag Khurana <ckhurana@codeaurora.org>
parent 8cc061c4

drivers/gpu/drm/msm/msm_kms.h

+7 −3
Original line number Diff line number Diff line
@@ -53,12 +53,16 @@ 
 */

/* Enable RGB444 30 bit deep color */

#define MSM_MODE_FLAG_RGB444_DC_ENABLE		(1<<5)

/* Enable YUV422 30 bit deep color */

#define MSM_MODE_FLAG_YUV422_DC_ENABLE		(1<<6)

/* Enable YUV420 30 bit deep color */

#define MSM_MODE_FLAG_YUV420_DC_ENABLE		(1<<6)

#define MSM_MODE_FLAG_YUV420_DC_ENABLE		(1<<7)

/* Choose RGB444 format to display */

#define MSM_MODE_FLAG_COLOR_FORMAT_RGB444	(1<<7)

#define MSM_MODE_FLAG_COLOR_FORMAT_RGB444	(1<<8)

/* Choose YUV422 format to display */

#define MSM_MODE_FLAG_COLOR_FORMAT_YCBCR422	(1<<9)

/* Choose YUV420 format to display */

#define MSM_MODE_FLAG_COLOR_FORMAT_YCBCR420	(1<<8)

#define MSM_MODE_FLAG_COLOR_FORMAT_YCBCR420	(1<<10)



/* As there are different display controller blocks depending on the

 * snapdragon version, the kms support is split out and the appropriate

drivers/gpu/drm/msm/sde/sde_encoder.c

+15 −3
Original line number Diff line number Diff line
@@ -199,6 +199,18 @@ static struct sde_csc_cfg sde_csc_10bit_convert[SDE_MAX_CSC] = { 
		{ 0x0040, 0x03ac, 0x0040, 0x03c0, 0x0040, 0x03c0,},

	},



	[SDE_CSC_RGB2YUV_709FR] = {

		{

			TO_S15D16(0x006d), TO_S15D16(0x016e), TO_S15D16(0x0025),

			TO_S15D16(0xffc5), TO_S15D16(0xff3b), TO_S15D16(0x0100),

			TO_S15D16(0x0100), TO_S15D16(0xff17), TO_S15D16(0xffe9),

		},

		{ 0x0, 0x0, 0x0,},

		{ 0x0040, 0x0200, 0x0200,},

		{ 0x0, 0x3ff, 0x0, 0x3ff, 0x0, 0x3ff,},

		{ 0x0, 0x3ff, 0x0, 0x3ff, 0x0, 0x3ff,},

	},



	[SDE_CSC_RGB2YUV_2020L] = {

		{

			TO_S15D16(0x0073), TO_S15D16(0x0129), TO_S15D16(0x001a),
@@ -5318,12 +5330,12 @@ void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc, 


	if (output_type == CDM_CDWN_OUTPUT_HDMI) {

		if (connector && connector->yuv_qs)

			csc_type = SDE_CSC_RGB2YUV_601FR;

			csc_type = SDE_CSC_RGB2YUV_709FR;

		else if (connector &&

			sde_connector_mode_needs_full_range(connector))

			csc_type = SDE_CSC_RGB2YUV_601FR;

			csc_type = SDE_CSC_RGB2YUV_709FR;

		else

			csc_type = SDE_CSC_RGB2YUV_601L;

			csc_type = SDE_CSC_RGB2YUV_709L;

	} else if (output_type == CDM_CDWN_OUTPUT_WB) {

		csc_type = SDE_CSC_RGB2YUV_601L;

	}

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+2 −0
Original line number Diff line number Diff line
@@ -792,6 +792,8 @@ static void sde_encoder_phys_vid_enable(struct sde_encoder_phys *phys_enc) 


	if (mode.private_flags & MSM_MODE_FLAG_COLOR_FORMAT_YCBCR420)

		fmt = sde_get_sde_format(DRM_FORMAT_YUV420);

	else if (mode.private_flags & MSM_MODE_FLAG_COLOR_FORMAT_YCBCR422)

		fmt = sde_get_sde_format(DRM_FORMAT_NV61);



	if (fmt) {

		struct sde_rect hdmi_roi;

drivers/gpu/drm/msm/sde/sde_hw_mdss.h

+1 −0
Original line number Diff line number Diff line
@@ -397,6 +397,7 @@ enum sde_csc_type { 
	SDE_CSC_RGB2YUV_601L,

	SDE_CSC_RGB2YUV_601FR,

	SDE_CSC_RGB2YUV_709L,

	SDE_CSC_RGB2YUV_709FR,

	SDE_CSC_RGB2YUV_2020L,

	SDE_CSC_RGB2YUV_2020FR,

	SDE_MAX_CSC

drivers/gpu/drm/msm/sde/sde_hw_top.c

+2 −2
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -159,7 +159,7 @@ static void sde_hw_setup_cdm_output(struct sde_hw_mdp *mdp, 
	if (cfg->wb_en)

		out_ctl |= BIT(24);

	else if (cfg->intf_en)

		out_ctl |= BIT(19);

		out_ctl |= BIT(28);



	SDE_REG_WRITE(c, MDP_OUT_CTL_0, out_ctl);

}